VCCIN_​AUX

FIVR Input rail: 1.8 V

VCC_​VNNEXT_​1P05

Used for FIVR PRIM_​CORE bypass mode during S0ix and Sx: 1.05 V

VCC_​V1P05EXT_​1P05

Used for FIVR PCH IO bypass mode during S0ix and Sx: 1.05 V

VCCA_​CLKLDO_​1P8

Analog supply for internal clocks: 1.8 V

VCCPRIM1P05_​OUT_​PCH

1.05 V Primary Well: for CNVi and other internal I/O blocks.

VCCDSW_​1P05

Deep Sx Well: 1.05 V. This rail is generated by on die DSW low dropout (LDO) linear regulator to supply DSW core logic.

VCCPRIM_​1P8

1.8 V Primary Well.

Note: When the VCCPRIM_​1P8 is off and the VCCPRIM_​3P3 is powered on during G3 to S5, there may be a leakage current from the VCCPRIM_​3P3 power rail to VCCPRIM_​1P8 power rail.

VCCPRIM_​3P3

3.3 V Primary Well.

VCCPGPPR

Audio Power 3.3 V or 1.8 V. If powered at 3.3 V, the 3.3 V supply can come from VCCPRIM_​3P3 supply. If powered at 1.8 V, the 1.8 V supply can come from VCCPRIM_​1P8 supply.

VCCDSW_​3P3

3.3 V Deep Sx Well.

VCCRTC

RTC Well Supply. This rail can drop to 2.0 V if all other planes are off. This power is not expected to be shut off unless the RTC battery is removed or drained.

VCCDPHY_​1P24

1.24 V for CNVi logic. This rail is generated internally with a LDO and needs to be routed to the motherboard so that the rail can be supplied back to the SoC.

VCCLDOSTD_​0P85

This rail is generated internally and needs to be routed out to the motherboard for decoupling purpose.

VCC1P05_​OUT_​FET

FIVR output rail: 1.05 V, used for CPU rails VCCST/STG.

VSSINAUX_​SENSE

VCCIN_​AUX VSS sense pin.

VCCINAUX_​SENSE

VCCIN_​AUX sense pin.

VSS

Ground