Intel® Core™ Processor (Series 3)
Formerly known as Wildcat Lake, Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 913965 | 05/19/2026 | 001 | Public |
Signal Description
| Signal Name | Type | Description |
|---|---|---|
| GPP_H19/I2C0_SDA/I3C0_SDA | I/OD | I3C Link 0 Serial Data Line External Pull-up resistor may be required depending on Bus Capacitance. |
| GPP_H20/I2C0_SCL/I3C0_SCL | I/OD | I3C Link 0 Serial Clock Line External Pull-up resistor may be required depending on Bus Capacitance. |
| GPP_H21/I2C1_SDA/I3C1_SDA | I/OD | I3C Link 1 Serial Data Line External Pull-up resistor may be required depending on Bus Capacitance. |
| GPP_H22/I2C1_SCL/I3C1_SCL | I/OD | I3C Link 1 Serial Clock Line External Pull-up resistor may be required depending on Bus Capacitance. |
| GPP_H10/UART0_RTS#/I3C1A_SDA/ISH_GP10A | I/OD | I3C Link 1A Serial Data Line External Pull-up resistor may be required depending on Bus Capacitance. Note : Alternate interface from/to the same I3C1 controller, to support touch device interface convergence. |
| GPP_H11/UART0_CTS#/I3C1A_SCL/ISH_GP11A | I/OD | I3C Link 1A Serial Clock Line External Pull-up resistor may be required depending on Bus Capacitance. Note : Alternate interface from/to the same I3C1 controller, to support touch device interface convergence. |
| GPP_F13/THC_I2C1_SDA/I3C2_SDA/THC1_SPI2_IO1/ISH_SPIA_MOSI/GSPI1_MISO/I2C5_SDA | I/OD | I3C Link 2 Serial Data Line External Pull-up resistor may be required depending on Bus Capacitance. |
| GPP_F12/THC_I2C1_SCL/I3C2_SCL/THC1_SPI2_IO0/ISH_SPIA_MISO/GSPI1_MOSI/I2C5_SCL | I/OD | I3C Link 2 Serial Clock Line External Pull-up resistor may be required depending on Bus Capacitance. |