Redirection Table Entry 0 (RTE0) – Offset 10 - 001 - ID:819324 | Intel® Core™ Ultra Processors for Edge (PS Series) SOC I/O Registers

Intel® Core™ Ultra Processors for Edge (PS Series) SOC I/O Registers

ID	Date	Version	Classification
819324	04/02/2024	001	Public

Redirection Table Entry 0 (RTE0) – Offset 10

*offset 10h - 11h

Bit Range	Default	Access	Field Name and Description
63:56	0h	RW	Destination ID (DID) Destination ID of the local APIC
55:48	0h	RW	Extended Destination ID (EDID) These bits are sent to a local APIC only when in Processor System Bus mode. They become bits 11:4 of the address.
47:17	0h	RO	Reserved
16	1h	RW	Mask field (MSK) When set, interrupts are not delivered nor held pending. When cleared, and edge or level on this interrupt results in the delivery of the interrupt.
15	0h	RW	Trigger Mode (TM) When cleared, the interrupt is edge sensitive. When set, the interrupt is level sensitive.
14	0h	RO/V	Remote IRR (RIRR) This is used for level triggered interrupts; its meaning is undefined for edge triggered interrupts. 0 = Reset when an EOI message is received that matches the VCT field. 1 = Set when IOxAPIC sends the level interrupt message to the CPU. Note, this bit is never set for SMI, NMI, INIT, or ExtINT delivery modes.
13	0h	RW	Polarity field (POL) This specifies the polarity of each interrupt input. When cleared, the signal is active high. When set, the signal is active low.
12	0h	RO/V	Delivery Status (DS) This field contains the current status of the delivery of this interrupt. When set, an interrupt is pending and not yet delivered. When cleared, there is no activity for this entry
11	0h	RW	Destination Mode (DSM) This field is used by the local Apic to determine whether it is the destination of the message.
10:8	0h	RW	Delivery Mode (DLM) This field specifies how the APICs listed in the destination field should act upon reception of this signal. Certain Delivery Modes will only operate as intended when used in conjunction with a specific trigger mode. 000: Fixed 001: Lowest Priority 010: SMI - Not supported 011: Reserved 100: NMI (Not supported) 101: INIT (Not supported) 110: Reserved 111: ExtINT
7:0	0h	RW	Vector field (VCT) This field contains the interrupt vector for this interrupt. Values range between 10h and FEh.