HSIO Power Management Configuration 2 (MODPHY_PM_CFG2) – Offset 10c4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
- CMU_ONE_DWORD25 (cmu_one_dword25)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
- DEVIDLE Control (HECI1_DEVIDLEC)
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
- Function Configuration (FNCFG)
Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
- Power Management Control (PMCTL)
Keyboard and Text (KT) Additional Configuration
- Power Management Control and Status (KT_CSXE_PMD_PMCSRBSE_PMCSR)
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Configuration
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
SATA MXTBA
SDXC (SD Card) PCR
- Dynamic Clock Gating Control (GPPRVRW1)
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

HSIO Power Management Configuration 2 (MODPHY_PM_CFG2) – Offset 10c4

Bit Range	Default	Access	Field Name and Description
30:16	-	-	Reserved
15:0	FFFFh	RW	HSIO Lane Sx SUS Well Power Gating Policy [15:0] (MLSXSWPGP) This is a bit per lane that controls SUS Well Power Gating for a HSIO lane when system is in Sx. Bit 0: Corresponds to HSIO Lane 0 Bit 1: Corresponds to HSIO Lane 1 Bit 2: Corresponds to HSIOLane 2 : : Bit 15: Corresponds to HSIO Lane 15 For each lane: 0: Lane power gating not permitted in Sx. 1: Lane power gating is permitted in Sx. Note that strap information/PCIe Lane reversal information will be factored by BIOS when programming these bits in the configuration registers. For ease of PMC implementation, this field will be used to manage Sx policies even in S0. In other words, the earlier restriction that BIOS does not have to program this field if MLSPDDGE is 1 does not apply any more. BIOS shall set this field appropriately for all cases.

Bit Range

Default

Access

Field Name and Description

30:16

Reserved

15:0

FFFFh

HSIO Lane Sx SUS Well Power Gating Policy [15:0] (MLSXSWPGP)

This is a bit per lane that controls SUS Well Power Gating for a HSIO lane when system is in Sx.

Bit 0: Corresponds to HSIO Lane 0

Bit 1: Corresponds to HSIO Lane 1

Bit 2: Corresponds to HSIOLane 2

:

:

Bit 15: Corresponds to HSIO Lane 15

For each lane:

0: Lane power gating not permitted in Sx.

1: Lane power gating is permitted in Sx.

Note that strap information/PCIe Lane reversal information will be factored by BIOS when programming these bits in the configuration registers.

For ease of PMC implementation, this field will be used to manage Sx policies even in S0. In other words, the earlier restriction that BIOS does not have to program this field if MLSPDDGE is 1 does not apply any more.

BIOS shall set this field appropriately for all cases.

HSIO Power Management Configuration 3 (MODPHY_PM_CFG3)

HSIO Power Management Configuration 1 (MODPHY_PM_CFG1) HSIO Power Management Configuration 3 (MODPHY_PM_CFG3)