PCIe* Device Reference Clock Request Mapping 2 (DRCRM2) – Offset 104 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
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Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
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High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
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I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
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Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
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Interrupt
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IO Trap
ISH
ISH PCH Configuration
ISH PCR
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Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
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PMC Memory Mapped
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Processor Interface Memory
PSF1
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PSF4
PSF5
RTC Indexed
RTC PCR
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SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
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SMBus PCR
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SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

PCIe* Device Reference Clock Request Mapping 2 (DRCRM2) – Offset 104

Bit Range	Default	Access	Field Name and Description
30	-	-	Reserved
29:25	01011b	RW/L	PCI Express Port 12 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 12.
24:20	01010b	RW/L	PCI Express Port 11 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 11.
19:15	01001b	RW/L	PCI Express Port 10 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 10.
14:10	01000b	RW/L	PCI Express Port 9 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 9.
9:5	00111b	RW/L	PCI Express Port 8 CLKREQ Mapping () Same description as bit [4:0], except that this field applies to PCIe Port 8.
4:0	00110b	RW/L	PCI Express Port 7 CLKREQ Mapping () The mapping of PCIe Port 7 to the corresponding CLKREQ# pin is configured by this field. 00h: Port 7 maps to CLKREQ0# pin. 01h: Port 7 maps to CLKREQ1# pin. ... 05h: Port 7 maps to CLKREQ5# pin. Others: Reserved Software must never map multiple PCIe Ports to the same CLKREQ# pin. The hardware behavior is undefined if this ever happens. Note:This field must be configured prior to enabling any power management features. Note: Configuring this field to map to any unsupported CLKREQ# pins may result in undefined hardware behavior. This register bit is Read-Only when the CC.SRL bit is set. Register Attribute: Static.

Device Reference Clock Request Mapping 3 (DRCRM3)

PCIe* Device Reference Clock Request Mapping 1 (DRCRM1) Device Reference Clock Request Mapping 3 (DRCRM3)