Intel® Core™ Ultra 200H and 200U Series Processors for Edge Platforms

Datasheet Addendum

ID Date Version Classification
847885 03/05/2025 001 Public
Document Table of Contents
Document Table of Contents
Legal and Disclaimers Revision History Introduction Thermal Management Display Graphics Enhanced Serial Peripheral Interface (eSPI) Power Management
Legal and Disclaimers
Revision History
Introduction
Introduction Terminology Reference Documents Supported Package and Die Plan
Terminology
Reference Documents
Supported Package and Die Plan
Thermal Management
Thermal Management Introduction Intel® Core™ Ultra Processor Line Thermal and Power Specifications
Thermal Management Introduction
Intel® Core™ Ultra Processor Line Thermal and Power Specifications
Display
Pipelock Bezel Correction
Pipelock
Overview
Overview
Bezel Correction
Graphics
SRIOV Overview Introduction Hardware Interface
SRIOV Overview
Introduction
Hardware Interface
Display Output from a Virtualized Environment GuC
Display Output from a Virtualized Environment
GuC
GuC Virtual Function Communication with GuC
Virtual Function Communication with GuC
Enhanced Serial Peripheral Interface (eSPI)
Enhanced Serial Peripheral Interface (eSPI) Functional Overview Pinlist
Functional Overview
Pinlist
Power Management
Power Management System Power Management System State G1/S3 State Transition Rules for the Processor
System Power Management
System State G1/S3
State Transition Rules for the Processor

Enhanced Serial Peripheral Interface (eSPI)

Note: For any capability not mentioned in this section, refer to Chapter 40 Enhanced Serial Peripheral Interface (eSPI) of Intel® Core™ Ultra 200H and 200U Series Processors Datasheet Volume 1 of 2 (RDC Document #842704)

1. Functional Overview

The eSPI controller supports up to 4 devices. The eSPI controller supports 20 MHz, 25 MHz, 33 MHz, and 50 MHz. An eSPI device can support frequencies lower than the recommended maximum frequency (50 MHz). In addition, the eSPI device must support a minimum frequency of 20 MHz for default (reset) communication between the host and device.

Second Target Device Presence

Note:The eSPI controller does not perform discovery to confirm the presence of the target connection. If a second device is enabled by soft strap, it must be physically present on the platform. If the second device is enabled by soft strap but is not physically present, the platform will fail to boot.

Signal Description

Signal Name Type Description Availability
GPP_​A13/ESPI_​CS1#/USB-C_​GPP_​A13 O eSPI Chip Select1: Driving CS# signallow to select eSPI device for the transaction. H/U Processor Line
GPP_​A14/ESPI_​CS2#/USB-C_​GPP_​A14 O eSPI Chip Select 2: Driving CS# signal low to selecteSPI device for the transaction. H/U Processor Line
GPP_​A15/ESPI_​CS3#/USB-C_​GPP_​A15 O eSPI Chip Select 3: Driving CS# signal low to selecteSPI device for the transaction. H/U Processor Line
GPP_​A16/ESPI_​ALERT0#/USB-C_​GPP_​A16 I

eSPI Alert 0: Alert signal from eSPI deviceto the Processor.

Note: If only a single device is connected, the eSPI Compatibility Specification requires that the device must operate with in-band Alert# signaling in order to free up the GPIO pin required for the discrete Alert# pin.

H/U Processor Line
GPP_​A17/ESPI_​ALERT1#/USB-C_​GPP_​A17 I

eSPI Alert 1: Alert signal from eSPI device to the Processor.

Note: If only a single device is connected, the eSPI Compatibility Spec requires that the device must operate with in-band Alert# signaling in order to free up the GPIO pin required for the discrete Alert# pin.

H/U Processor Line
GPP_​A18/ESPI_​ALERT2#/USB-C_​GPP_​A18 I

eSPI Alert 2: Alert signal from eSPI device to the Processor.

Note: If only a single device is connected, the eSPI Compatibility Spec requires that the device must operate with in-band Alert# signaling in order to free up the GPIO pin required for the discrete Alert# pin.

H/U Processor Line
GPP_​A19/ESPI_​ALERT3#/USB-C_​GPP_​A19 I

eSPI Alert 3: Alert signal from eSPI device to the Processor.

Note: If only a single device is connected, the eSPI Compatibility Spec requires that the device must operate with in-band Alert# signaling in order to free up the GPIO pin required for the discrete Alert# pin.

H/U Processor Line

Integrated Pull-Ups and Pull-Downs

Signal Resistor Type Value Notes
ESPI_​CS [3:0] # Pull-up 20 kohm +/- 30%
ESPI_​ALERT [3:0] # Pull-up 20 kohm +/- 30%

I/O Signal Planes and States

Signal Name Power Plane During Reset Immediately after Reset1 S4/S5
ESPI_​CS [3:0] # Primary Internal Pull-up Driven High Driven High
ESPI_​ALERT [3:0] # Primary Internal Pull-up Driven High Driven High
Note:1. Reset reference for primary well pins is RSMRST#.

Functional Overview