Problem

When doing a hotplug on a USB hub with two or more USB Full-speed or Low-speed devices each with a 1 ms service interval interrupt endpoint, a race condition may occur between the PMC and the xHCI controller.

Implication

The processor may fail to enter C3 or deeper package C-States. Note: This erratum has only been observed in a synthetic environment.

Workaround

None identified. This condition is recovered after the xHCI controller has successfully entered D3.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On USB 3.2 Gen 1x1 only capable ports, including ports configured as USB 3.2 Gen 1x1 by soft strap, the xHCI controller may send only 15 LFPS signals instead of a burst of 16 LFPS signals as specified by the USB 3.2 specification.

Implication

There are no known functional implications due to this erratum. LFPS handshake requires the receiver link partner to only detect 2 LFPS signals. This issue may impact the SuperSpeed compliance test case which checks for the 16 LFPS burst requirements: TD6.4, TD6.5, and TD7.31.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the I²S interface is in device mode, the audio controller may not be correctly configured if the audio codec requires high frame polarity.

Implication

Due to this erratum, the left and right audio channels may swap when frame polarity is set to high.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A delay in the availability of LCRD1 (Link Credit 1) from a USB 3.2 hub, with two or more downstream USB 3.2 bulk endpoint devices engaged in SuperSpeedPlus concurrent transfers, may lead to the connected xHCI controller sending the ACK and Status of a transfer packet out of order.

Implication

Due to this erratum, a USB 3.2 bulk endpoint device may not respond to subsequent transfers. It may be possible for a device driver to recover the USB 3.2 device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The PTM Propagation Delay Adaptation Interpretation B (PTMPDAIB) Bit is implemented at Configuration Space (CFG) Offset 158h instead of at 50h as documented in the PCI-SIG PTM Byte Ordering Adaptation Engineering Change Notice (ECN).

Implication

End Point Device (EPD) software that implements the PTM Byte Ordering Adaptation ECN will not be able to program their PTMPDAIB Bit correctly since it is located at a different register offset.

Workaround

None identified. To mitigate this issue, EPD software that implements the PTM Byte Ordering Adaptation ECN must access PTMPDAIB at CFG Offset 158h.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On systems with dual IO mode enabled, SPI0_​IO2 and SPI0_​IO3 may momentarily drive low before these signals are pulled high by internal resistors during boot from the G3 state.

Implication

Due to this erratum, unexpected system behavior may occur on systems when SPI0_​IO2 and SPI0_​IO3 signals are connected to an SPI device.

Workaround

None identified. To mitigate this erratum, do not connect SPI0_​IO2 and SPI0_​IO3 to an SPI device in SPI0 dual IO mode enabled systems.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Disconnecting a USB full-speed device from the USB port while the xHCI controller is in the process of sending the Start of Frame may cause the USB 2.0 functionality to become unresponsive for that specific port.

Implication

Due to this erratum, USB 2.0 devices may not be recognized on the USB port until a host controller reset occurs. Intel has only observed this behavior in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

An internal memory decode error may occur when software attempts to access the last byte of a 4 KB page boundary within the LPC Generic Memory Range (LGMR) using memory read/write commands of sizes 8, 16, 32, or 64 bytes.

Implication

Due to this erratum, the system may hang with a FATAL_​ERROR message reported on the Direct eSPI interface.

Workaround

None identified. A mitigation for this erratum is available by doing one of the following:1. To access the last byte, software should separate the read/write commands into multiple lengths of 4/2/1 bytes.2. Software should always use 4 byte read/write commands when accessing LGMR.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When multiple USB 2.0 split transaction errors occur, the xHCI host controller may become unresponsive.

Implication

Due to this erratum, USB devices connected to the xHCI controller may not function.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the xHCI controller is stressed with concurrent traffic across multiple USB ports, the xHCI controller may fail to service USB 2.0 Isochronous IN endpoints within the required service interval.

Implication

USB 2.0 isochronous devices connected to the xHCI controller may experience dropped packets.Note: This issue has only been observed with a USB 3.2 Bulk Stream device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The following clock timing specifications of Serial IO and Integrated Sensor Hub (ISH) I3C interfaces may not meet the minimum timing requirements listed in the MIPI specification version 1.0:

• Serial IO and ISH: SCL and SDA fall time when operating in I2C mode for Fast Mode (400 Kbps) and Fast Mode Plus (1 Mbps) speeds. 

• Serial IO and ISH: SCL rise time when operating in I2C mode for Fast Mode (400 Kbps). 

• Serial IO: SCL low time when operating in I2C mode for Fast Mode (400 Kbps) and Fast Mode Plus (1 Mbps) speeds.

Implication

There are no known functional implications due to this erratum and Intel has not observed this erratum with any commercially available system.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.