Summary Tables of Changes

12th Generation Intel® Core™ Processor

Specification Update

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ID 682436

Date 01/05/2022

Version

Public

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The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed processor stepping. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. This table uses the following notations:

Codes Used in Summary Table

Stepping	Description
(No mark) or (Blank Box)	This erratum is fixed in listed stepping or specification change does not apply to listed stepping.

Status	Description
Doc	Document change or update that is implemented.
Planned Fix	This erratum may be fixed in a future stepping of the product.
Fixed	This erratum has been previously fixed in Intel hardware, firmware, or software.
No Fix	There are no plans to fix this erratum.

Errata Summary Table

ID	Processor Line			Title
ID	S	H	U	Title
ADL001	No Fix	No Fix	No Fix	X87 FDP Value May be Saved Incorrectly
ADL002	No Fix	No Fix	No Fix	Debug Exceptions May Be Lost or Misreported When MOV SS or POP SS Instruction is Not Followed By a Write to SP
ADL003	No Fix	No Fix	No Fix	VMREAD/VMWRITE Instructions May Not Fail When Accessing an Unsupported Field in VMCS
ADL004	No Fix	No Fix	No Fix	BMI1, BMI2, LZCNT, ADXC, and ADOX Instructions May Not Generate an #UD
ADL005	No Fix	No Fix	No Fix	Exit Qualification For EPT Violations on Instruction Fetches May Incorrectly Indicate That The Guest-physical Address Was Writeable
ADL006	No Fix	No Fix	No Fix	Processor May Generate Spurious Page Faults On Shadow Stack Pages
ADL007	No Fix	No Fix	No Fix	Processor May Hang if Warm Reset Triggers During BIOS Initialization
ADL008	No Fix	No Fix	No Fix	System May Hang When Bus-Lock Detection Is Enabled And EPT Resides in Uncacheable Memory
ADL009	No Fix	No Fix	No Fix	Processor May Generate Malformed TLP
ADL010	No Fix	No Fix	No Fix	No #GP Will be Signaled When Setting MSR_MISC_PWR_MGMT.ENABLE_SDC if MSR_MISC_PWR_MGMT.LOCK is Set
ADL011	N/A	N/A	N/A	N/A. Erratum has been removed.
ADL012	No Fix	No Fix	No Fix	Last Branch Records May Not Survive Warm Reset
ADL013	No Fix	No Fix	No Fix	PCIe Link May Fail to Train Upon Exit From L1.2
ADL014	No Fix	No Fix	No Fix	Incorrectly Formed PCIe Packets May Generate Correctable Errors
ADL015	No Fix	No Fix	No Fix	#UD May be Delivered Instead of Other Exceptions
ADL016	N/A	No Fix	No Fix	Type-C Host Controller Does Not Support Certain Qword Accesses
ADL017	No Fix	No Fix	No Fix	#GP May be Serviced Before an Instruction Breakpoint
ADL018	No Fix	No Fix	No Fix	Unexpected #PF Exception Might Be Serviced Before a #GP Exception
ADL019	No Fix	No Fix	No Fix	WRMSR to Reserved Bits of IA32_L3_QOS_Mask_15 Will Not Signal a #GP
ADL020	No Fix	No Fix	No Fix	VMX-Preemption Timer May Not Work if Configured With a Value of 1
ADL021	No Fix	No Fix	No Fix	Setting MISC_FEATURE_CONTROL.DISABLE_THREE_STRIKE_CNT Does Not Prevent The Three-strike Counter From Incrementing
ADL022	N/A	N/A	N/A	N/A. Erratum has been removed.
ADL023	No Fix	No Fix	No Fix	Unable to Transmit Modified Compliance Test Pattern at 2.5 GT/S or 5.0 GT/s Link Speeds
ADL024	Fixed	N/A	N/A	Single Core Configurations May Hang on S3/S4 Resume
ADL025	No Fix	No Fix	No Fix	Single Step on Branches Might be Missed When VMM Enables Notification On VM Exit
ADL026	No Fix	No Fix	No Fix	Reading The PPERF MSR May Not Return Correct Values
ADL027	No Fix	No Fix	No Fix	Incorrect #CP Error Code on UIRET
ADL028	Fixed	Planned Fix	Planned Fix	Processor May Not Wake From TPAUSE/UMWAIT in Limited Situations
ADL029	Fixed	Planned Fix	Planned Fix	Platform May Not Resume From G3/S3/S4/S5
ADL030	No Fix	No Fix	No Fix	Intel^® Processor Trace PSB+ Packets May Contain Unexpected Packets
ADL031	No Fix	No Fix	No Fix	Intel^® PT Trace May Drop Second Byte of CYC Packet
ADL032	No Fix	No Fix	No Fix	VM Entry That Clears TraceEn May Generate a FUP
ADL033	No Fix	No Fix	No Fix	Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results
ADL034	N/A	No Fix	No Fix	Processor May Hang When PROCHOT# is Active
ADL035	No Fix	No Fix	No Fix	CPUID Reports Incorrect Number of Ways For The Load DTLB
ADL036	Fixed	Fixed	Fixed	Unaligned CET-SS Stack Token Does Not Signal #GP
ADL037	No Fix	No Fix	No Fix	Intel^® PT Trace May Contain Incorrect Data When Configured With Single Range Output Larger Than 4KB
ADL038	No Fix	No Fix	No Fix	OFFCORE_REQUESTS_OUTSTANDING Performance Monitoring Events May be Inaccurate
ADL039	No Fix	No Fix	No Fix	On Instructions Longer Than 15 Bytes, #GP Exception is Prioritized And Delivered Over #CP Exception
ADL040	No Fix	No Fix	No Fix	Mismatch on DR6 Value When Breakpoint Match is on Bitmap Address
ADL041	No Fix	No Fix	No Fix	Processor Loads PERF_GLOBAL_CTRL MSR Value From SMM Transfer VMCS Upon STI When STM is Configured
ADL042	No Fix	No Fix	No Fix	RTM Abort Status May be Incorrect For INT1/INT3 Instructions

Specification Changes

No.	Specification Changes
	None for this revision of this specification update.

Specification Clarifications

No.	Specification Clarifications
	None for this revision of this specification update.

Documentation Changes

No.	Documentation Changes
	None for this revision of this specification update.