Problem

When sending a SATA enclosure LED message and all SATA ports are either idle or disabled, the PCH may not transmit the LED message due to an internal clock gating issue.

Implication

The LED status for SATA enclosure may be incorrect.

Workaround

None identified. Enclosure Management SW can poll the Enclosure Management (EM_​CTL) - Offset 20h bit 8 register for a 0 value immediately before writing LED messages.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The IOSF-SB eSPI Link Configuration Lock (SBLCL) bit (offset 4000h, bit 27 in eSPI PCR space) is reset by RSMRST# assertion instead of PLTRST# assertion.

Implication

If the SBLCL bit is set to 1, software will not be able to access the eSPI device Capabilities and Configuration register in the reserved address range (0h - 7FFh) until RSMRST# asserts.

Workaround

If software needs to access the eSPI device reserved range 0h - 7FFh while SBLCL bit is set to 1, a RSMRST# assertion should be performed.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The PCIe Clock Output signals (CLKOUT_​PCIE_​P/N) and PCIe reference clock signals to processor (CLKOUT_​CPUPCIBCLK_​P/N) may not meet the maximum Rising/Falling Edge Rate and VCROSS specifications as defined in the PCI Express Card Electromechanical Specification Revision 3.0, section 2.1.3, REFCLK AC Specifications.

Implication

There are no known functional failures due to this erratum.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If USB audio offload is enabled for a USB Full-Speed Isochronous audio device connected behind a USB 2.0 or later hub and there is an active concurrent bulk transfer to another device on any port of the xHCI controller or behind the hub, the controller may stall the offloaded audio traffic and a split transaction error may occur.

Implication

The USB audio offload playback may stop. Audio may be recovered if the audio stream is paused and restarted, the audio device is removed and reconnected, or the audio application is restarted.

Workaround

None identified. A mitigation for this erratum is available with a combination of Microsoft Windows 11 OS Release and Intel® Smart Sound Technology version 10.29.00.5574 or later. This mitigation will disable audio offload functionality for USB audio devices connected behind a hub.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Upon GbE controller D3 exit, the GbE host driver performs a controller reset. During this reset, software accesses to the GbE MMIO registers may not complete.

Implication

The system may hang.

Note: This erratum has only been observed in a synthetic environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI Host Controller reports the value of 0h for the Link Protocol (LP) bits [15:14] in register XECP_​SUPP_​USB3_​6 (MMIO offset 8038h) and XECP_​SUPP_​USB3_​7 (MMIO offset 803Ch), which does not meet the xHCI specification revision 1.2.

Implication

There are no known functional failures due to this erratum.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller does not return the correct completion code for the Force Header Command as defined in the Section 4.6.16 of the eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Requirements Specification Rev 1.2.

Implication

xHCI CV TD4.12 - Force Header Command Test may report an error. Intel has obtained a waiver for TD 4.12. The Force Header Command is only used by the USB-IF Command Verifier (xHCI CV) tool for device testing. There are no known functional failures due to this erratum.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI spec version 1.2 defines the PCI Express Capability structure offset 04h Device Capabilities (DVSEC) field to be 8 bytes. The USB Virtualization Based Trusted IO (VTIO) Management controller implements the DVSEC field as 12 bytes.

Implication

An USB controller driver may not be able to enable the USB VTIO controller.

Workaround

None identified. To mitigate this erratum, an Independent Software Vendor could account for the field length in the USB controller driver.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Setting the Disable SLP_​X Stretching After SUS Well Power Up (DIS_​SLP_​X_​STRCH_​SUS_​UP) bit (offset 1020h, bit 12 in PMC_​MMIO space) to 1 does not disable the SLP_​A# Minimum Assertion Width (SLP_​A_​MIN_​ASST_​WDTH) timer (offset 1020h, bit 17 and 16 in PMC_​MMIO space).

Implication

G3 exit duration may be extended by the value programmed in the SLP_​A_​MIN_​ASST_​WDTH register.

Workaround

None identified. To mitigate the issue for platforms that do not require SLP_​A# stretching, BIOS should program SLP_​A_​MIN_​ASST_​WDTH to 0.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a USB Full-speed or Low-speed (with an Interrupt IN Endpoint) device is connected behind a USB hub and a USB bulk device is also connected to any port on the xHCI controller, a split transaction error may occur on the USB Full-speed or Low-speed device.

Implication

The USB Controller driver may reset the USB Full-speed or Low-speed Interrupt IN Endpoint. The observed behavior is USB device specific. For example, a delay in response may be observed from a Low-speed USB mouse or keyboard device.

Workaround

A BIOS code change has been identified and may be implemented as a workaround for this erratum.For a more power optimized solution, a xHCI controller driver may dynamically clear the xHCI MMIO offset 0x8144 bit 8 when a USB Full-speed or Low-speed device is not connected behind a USB Hub and ensure the bit is set as configured by the BIOS.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Following a RTC Reset the PCH debug subsystem may enter an unsupported state if Delayed Authentication Mode (DAM) and DCI are disabled.Note: This issue may be observed only from PMC version 160.02.00.1029 to 160.02.00.1031.

Implication

The system may hang while exiting G3 and requires reflashing the system IFWI to recover.

Workaround

A BIOS code change has been identified and may be implemented as a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If a USB 3.2 Gen 1x1 hub sends an upstream truncated packet with DPPABORT OS (Data Packet Payload Abort Order Set) framing followed by an ACK packet for a previous OUT transfer from the xHCI controller, the ACK packet may be dropped by the xHCI controller.

Implication

A timeout may be observed for the OUT transfer packet. Per the xHCI spec, a xHCI controller driver will issue a warm port reset to the device causing a device re-enumeration.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When doing a hotplug on a USB hub with two or more USB Full-speed or Low-speed devices each with a 1 ms service interval interrupt endpoint, a race condition may occur between the PMC and the xHCI controller.

Implication

The processor may fail to enter C3 or deeper package C-States. Note: This erratum has only been observed in a synthetic environment.

Workaround

None identified. This condition is recovered after the xHCI controller has successfully entered D3.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a Timed GPIO event is counted in the Event Counter Capture (TGPIOECCV) register (offset 1238h, bits 31 to 0 in PWRMBASE space), the Time Capture (TGPIOTCV) register (offset 1230h, bits 31 to 0 in PWRMBASE space) value is not immediately updated after that event is counted.

Implication

A Timed GPIO event may have a mismatched time stamp.

Workaround

None identified. A Timed GPIO driver can partially mitigate for this erratum by detecting that a TGPIOECCV register change has occurred without a TGPIOTCV register change and then repeatedly re-read the TGPIOTCV register until a change does occur.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On USB 3.2 Gen 1x1 only capable ports, including ports configured as USB 3.2 Gen 1x1 by soft strap, the xHCI controller may send only 15 LFPS signals instead of a burst of 16 LFPS signals as specified by the USB 3.2 specification.

Implication

There are no known functional implications due to this erratum. LFPS handshake requires the receiver link partner to only detect 2 LFPS signals. This issue may impact the SuperSpeed compliance test case which checks for the 16 LFPS burst requirements: TD6.4, TD6.5, and TD7.31.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When USB 2.0 DCI.DBC is enabled and the DCI.DBC connection is established, a race condition may prevent the xHCI controller from correctly exiting the U1 or U2 link state.

Implication

A USB 3.2 device may get re-enumerated if the USB device initiates a U1 or U2 link state exit.

Workaround

A BIOS code change has been identified and may be implemented as a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.