Feature Set

• SprLUT feature - SprLUT was added for complex non-linear activation functions.
• Optimized HW support for standard and depth-wise convolutions,
• Convolution Kernel size of M*N where N, M are up to 11,
• Convolution Stride of up to 8,
• Support configurable padding of activations,
• Supports reuse of activations and weights to reduce CMX Memory read bandwidth,
• Support for both Dense and Sparse operations,
• Sparse Element-wise operations,
• Supported Data Types
  • FP8
  • I8
  • U8

• Precision
  • FP32 and INT32 accumulators
  • Floating point and integer scaling supported
  • Integer floating point inline conversion
  • Floating point subnormal support
• Supports statistics gathering (Hardware Profiling)
• Features 64 Post Processing Elements (PPE) where each support:
  • Quantization
  • Activation function
  • Element-Wise functions

• Features Four 256-bit wide Read-Only Ports and four 256-bit wide Read/Write Ports
• Support for Sparse acceleration and compression to increase effective TOPs by up to 2x.
  • Sparsity awareness allows the MAC circuits to run more TOPs by not consuming cycles processing data that does not affect the result.
  • Those extra (or effective) TOPs translate to lower power for the same compute performance, or, higher compute performance for the same power by comparison to a design that is sparsity agnostic.
• DPU State Machine is responsible for loading tensor workloads and micro-scheduling.
• New Feature in NPU that allows splitting Input channels (ICs) across MPE to improve the overall utilization of the PE array.