GNR1. Intel® VT-d Remapping Hardware Does Not Perform Reserved(0) Check on PGSNP Field of Scalable-Mode PASID Table Entry

Problem: Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) remapping hardware does perform Reserved(0) check on Page Snoop (PGSNP) field in scalable-mode Process Address ID (PASID) table entry when Snoop Control capability is defined as not available in the Extended Capability Register Offset 10h bit 7 (ECAP.SC=0).

Implication: There are no known functional implications due to this erratum. Intel has not observed this erratum with any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR2. Remapping Hardware May Set Access/Dirty Bits in a First-Stage Page-Table Entry

Problem: When remapping hardware is configured by system software in scalable mode as Nested (PGTT=011b) and with PWSNP field Set in the PASID-table-entry, it may Set Accessed bit and Dirty bit (and Extended Access bit if enabled) in first-stage page-table entries even when second-stage mappings indicate that corresponding first-stage page-table is Read-Only.

Implication: Due to this erratum, pages mapped as Read-only in second-stage page-tables may be modified by remapping hardware Access/Dirty bit updates.

Workaround: None identified. System software enabling nested translations for a VM should ensure that there are no read-only pages in the corresponding second-stage mappings.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR3. Machine Check Bank 4 UCNA Errors May Not Be Signaled

Problem: When any UC error is not enabled in machine check bank 4 due its associated bit being 0 in IA32_​MC4_​CTL (MSR 410h), and the disabled UC error and a UCNA error happen simultaneously, the UC error is logged with overflow set, but the UCNA error may not be signaled.

Implication: Due to this erratum, when UC errors are disabled in bank 4, UCNA errors may not be signaled.

Workaround: None identified. Software should keep MCAs enabled in IA32_​MC4_​CTL.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR4. Platform May Hang if System Software Sends a Page Group Response or DevTLB Invalidation to Non-existent Requester ID

Problem: When system software submits a Page Group Response or DevTLB Invalidation command to remapping hardware, the remapping hardware forwards commands to Root-Complex so that the Root-Complex may route the command to Requester ID specified by system software. If system software specifies a Requester ID in the command that does not exist on the platform, the command is not correctly aborted and may cause the system to hang.

Implication: If system software issues a Page Group Response or DevTLB Invalidations towards Requestor ID that does not exist on the platform, the system may hang. Intel has only observed this behavior in a synthetic test environment.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR5. Remapping Hardware Implements Bits [31:16] of the three Event Data Registers (VTDBAR offsets 0x3C, 0xA4, and 0xE4) as Read-Writable

Problem: Bits [31:16] of the three Event Data registers (VTDBAR offsets 0x3C, 0xA4, and 0xE4) are defined to be “Reserved and Zero” (RsvdZ) but are implemented as Read-Writable (RW).

Implication: Due to this erratum, system software may write these bit[31:16] to non-zero values. Intel has not observed this erratum to impact the operation of any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR6. Processor May Hang if Warm Reset Triggers During BIOS Initialization

Problem: Under complex micro-architectural conditions, when the processor receives a warm reset during BIOS initialization, the processor may hang with a machine check error reported in IA32_​MCi_​STATUS, with MCACOD (bits [15:0]) value of 0400H, and MSCOD (bits [31:16]) value of 0080H.

Implication: Due to this erratum, the processor may hang. Intel has only observed this erratum in a synthetic test environment.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR7. Unexpected Rollover in MBM Counters

Problem: When using Intel® Resource Director Technology (Intel® RDT), unexpected rollover can occur when Memory Bandwidth Monitoring (MBM) counter values are close to the the maximum allowed counter value. A rollover is when a MBM counter value read in the n+1th iteration is lower than nth iteration..

Implication: Due to this erratum, bandwidth computed from successive MBM readings representing a rollover may not be accurate.

Workaround: None identified. Software should discard the memory bandwidth computed over a rollover interval.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR8. Remapping Hardware May Encounter Incorrect Error Code in Invalidation Queue Error Record Register

Problem: When fetching a new descriptor from the Invalidation Queue, if DMA remapping hardware observes an unsupported value in the Translation Table Mode (TTM) field, it may report an invalid descriptor width programmed in the InvalidationQueue (code 5) instead of invalid value in the TTM field of the Root Table Address (code 7) in the Invalidation Queue Error Info (IQEI) register of the IQERCD_​REG (VTDBAR offset 0xB0).

Implication: Due to this erratum, Software that distinguishes between error code 5 and error code 7 may not function as expected.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR9. Performance Monitoring events TOPDOWN.BACKEND_​BOUND_​SLOTS and IDQ_​BUBBLES may be inaccurate.

Problem: The performance monitoring events TOPDOWN.BACKEND_​BOUND_​SLOTS (Event A4h, UMask 02h) and IDQ_​BUBBLES.* (Event 9Ch, UMask 01h) may not count when the processor is in the C0.2 power sub-state, which is entered via the TPAUSE or UWAIT instructions. This erratum also impacts the accuracy of MSR_​PERF_​METRICS fields Frontend Bound, Backend Bound, and Fetch Latency (MSR 329h, Bits [23:16], [31:24] and [55:48]).

Implication: Due to this erratum, these performance monitoring events and the fields in MSR_​PERF_​METRICS may be inaccurate.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR10. Performance Monitoring Event IDQ.MS_​UOPS May Undercount

Problem: The performance monitoring events IDQ.MS_​UOPS, IDQ.MS_​SWITCHES, and IDQ.MS_​CYCLES_​ANY (Event 79h, UMask 30h) may undercount MS_​UOPS that come from the Decode Stream Buffer (DSB).

Implication: Due to this erratum, performance monitoring counters may report counts lower than expected.

Workaround: None identified. Performance monitoring event UOPS_​RETIRED.MS may be used instead.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR11. TILEDATA State May Be Saved Incorrectly

Problem: If execution of XRSTOR or XRSTORS causes a fault or a VM exit, a subsequent execution of XSAVE, XSAVEC, XSAVEOPT, or XSAVES instructions may incorrectly save the TILEDATA state component as all zeroes. This will occur only if the execution of XRSTOR or XRSTORS is attempting to set the TILECFG state component to its initial configuration and to restore the TILEDATA state component from the XSAVE area in memory..

Implication: Due to this erratum, the data saved in the XSAVE area for the TILEDATA state may be incorrect.

Workaround: None identified. Following an execution of XRSTOR or XRSTORS that causes a fault or a VM exit, software should not use the TILEDATA state component saved by a subsequent execution of XSAVE, XSAVEC, XSAVEOPT, or XSAVES that occurs before re-executing the original instruction (after addressing the cause of the fault or VM exit).

Status: For the steppings affected, see the Summary Tables of Changes.

GNR12. RDT MBM May Overcount Memory Bandwidth Measurements

Problem: The Intel® Resource Director Technology (RDT) Memory Bandwidth Monitor (MBM) feature may overcount memory bandwidth measurements when both the Dead Block predictor and the Last Level Cache stream prefetcher are enabled.

Implication: Due to this erratum, software that relies upon the MBM counters may function incorrectly.

Workaround: None identified. Software may use alternatively use uncore performance monitoring of UNC_​M_​CAS_​COUNT_​SCH0.RD, UNC_​M_​CAS_​COUNT_​SCH0.WR, UNC_​M_​CAS_​COUNT_​SCH1.RD, and UNC_​M_​CAS_​COUNT_​SCH1.WR to measure aggregate memory bandwidth. For more information, refer to https://perfmon-events.intel.com.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR13. Intel® QAT Accelerator May Violate ATS Invalidation Completion Ordering

Problem: Address Translation Service (ATS) invalidations may complete before all in-flight writes are drained from Intel® QuickAssist Technology (Intel® QAT) accelerator.

Implication: Due to this erratum, Intel QAT accelerator operation with ATS capability enabled may lead to unexpected system behavior.

Workaround: None identified. System software (OS/VMM) performing ATS invalidation on Intel QAT accelerator needs to serially execute a second (duplicate) ATS invalidation request after the first invalidation completes to drain in-flight writes.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR14. Intel QAT Accelerator Device May Not Invalidate PASID Supervisor-Privilege Translations

Problem: ATS invalidations for Process Address Space ID (PASID) with Supervisor-privilege translations may not correctly invalidate the device TLB on Intel QAT.

Implication: Due to this erratum, Intel QAT accelerator operation with ATS capability enabled and Supervisor-privilege PASID may lead to unexpected system behavior.

Workaround: None identified. System software (OS/VMM) performing ATS invalidation on Intel QAT accelerator on behalf of any supervisor-privilege PASID must set the Global Invalidate (G) bit in the ATS invalidation to avoid the erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR15. RTTO May Occur at Lower Link Speed And Reduce Link Width

Problem: When a 32 GT/s, x16 PCI Express* (PCIe*) port is configured to operate at a lower link speed and reduced link width (such as 2.5 GT/s, x1 mode), Data Link Layer Packets (DLLPs), including transaction ACK packets, may incur large latencies.

Implication: Due to this erratum, large latencies at lower link speeds and reduced link widths may lead to Replay Timer Timeout (RTTO) failures from the link partner.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR16. PCIe* Root Port May Fail to Set The RICFM Bit

Problem: The PCIe Root Port may not set the Received Integrity Check Fail Message (RICFM) bit in the Selective IDE Stream Status Register (Bit [31] in SIDESSTS_​1,Bus: 29, 28, 26, 5-1; Device: 9-2; Function: 0; Offset 320h) when the Root Port receives an Integrity Data Encryption (IDE) Fail message from a PCIe device.

Implication: Due to this erratum, when the Root Port receives an IDE Fail message from a PCIe device, software that relies upon the RICFM bit may function as expected.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR17. Intel® IAA Drop Initial Bits Field in AECS May Not Clear When Drop Initial Bits field is 8 Times Source1 Size

Problem: On systems with Intel® In-Memory Analytics Accelerator (Intel® IAA) enabled, if the Drop Initial Bits field (Offset 1DCh) in the Analytics Engine Configuration and State (AECS) structure is equal to 8 times the Source 1 Transfer Size (Offset 20h) in the descriptor, then if the AECS is written out at the end of a decompression job, the updated value of this Drop Initial Bits field is incorrect.

Implication: Due to this erratum, if AECS is used to pass information between related jobs and this condition occurs, the following job may generate incorrect output, which may lead to unpredictable system behavior.

Workaround: None identified. If this condition occurs, then when the job completes, software must manually zero the Drop Initial Bits field.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR18. Intel IAA/Intel® DSA May Not Report Interrupt PASID Check Failure Error

Problem: On systems with Intel IAA or Intel® Data Streaming Accelerator (Intel® DSA), if Drain Descriptor encounters both an Interrupt PASID check failure and a Page Fault error on an explicit readback address, the interrupt PASID check failure may not be reported.

Implication: Due to this erratum, software that relies on the interrupt PASID check failure error being reported may not function as expected.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR19. The Processor May Drop Noncompliant Posted Peer-to-Peer Transactions

Problem: If the processor receives a noncompliant posted PCIe peer-to-peer transaction with non-zero upper tag bits [9:8], it may drop the transaction instead of forwarding it to the intended destination.

Implication: Due to this erratum, PCIe devices that perform peer-to-peer posted transactions may not operate as expected. Intel has not observed this erratum with any commercially available devices.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR20. Single Step on Branches Might be Missed When VMM Enables Notification On VM Exit

Problem: Under complex micro-architectural conditions, "single step on branches" (configured when IA32_​DEBUGCTLMSR (Offset 1D9h, bit [1]) and TF flag in EFLAGS register are set) while in guest might be missed when VMM enables "notification on VM Exit" (IA32_​VMX_​PROCBASED_​CTLS2 MSR, Offset 48Bh, bit [31]) while the dirty access bit is not set for the code page (bit [6] in paging-structure entry)..

Implication: Due to this erratum, when "single step on branches" is enabled under the above condition, some single step branches will be missed. Intel has only observed this erratum in a synthetic test environment.

Workaround: None identified. When enabling single step on branches for debugging, software should first set the dirty bit of the code page.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR21. Remapping Hardware May Not Generate a Page Request Group Response Message While Operating in Legacy Mode or Abort DMA Mode

Problem: Remapping hardware may not generate a Page Request Group Response Message while operating in Legacy mode or Abort DMA mode if a PCIe device generates a Page Request Message.

Implication: Due to this erratum, when the remapping hardware fails to generate a Page Request Group Response Message may lead to unpredictable device behavior, including a device hang. The remapping hardware continues to report RTA.3 or RTA.4 faults if it receives these Page Request Group Response Message. Intel has only observed this behavior in a synthetic test environment.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR22. Remapping Hardware May Abort ZLR to Second-Stage Write Only Pages

Problem: Remapping hardware reports non-recoverable Intel VT-d fault and causes the Zero-Length-Read (ZLR) to be aborted, If a ZLR encounters read-only page in first-stage tables and write-only page in second-stage tables.

Implication: Due to this erratum, device may observe an unexpected abort on a ZLR and an Intel VT-d fault may be indicated. Intel has not observed this erratum with any commercially available software.

Workaround: None identified. System software should not create write only pages in second-stage page tables.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR23. Remapping Hardware Does Not Perform Reserved (0) Check in Page Response Descriptor

Problem: Remapping hardware does not set Invalidation Queue Error field in the Fault Status Register (VTDBAR offset 0x34) when software writes non-zero value in bits [255:128] and bit[5] of the Page Response descriptor.

Implication: System software violating Intel VT-d architecture requirement by programming non-zero values in bits [255:128] and bit[5] of Page Response descriptor may not fault on current processors but may fault on future processors. Intel has not observed this sighting/erratum with any commercially available system.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR24. The Time-Stamp Counter May Report an Incorrect Value

Problem: Under complex micro-architectural conditions, the Time-Stamp Counter (TSC) may incorrectly report the time stamp to be less than the expected time stamp after exiting C6 power saving state.

Implication: Due to this erratum, systems that rely upon a monotonically increasing value reported by the TSC may exhibit unpredictable system behavior.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR25. CHA UCNA Errors May Be Incorrectly Controlled by MC7_​CTL Enable Bits

Problem: Uncorrectable Error No Action required (UCNA) errors reported in Cache Home Agent (CHA) Machine Check Banks (Bank 7) IA32_​MC7_​STATUS (MSR 41Dh) may be incorrectly controlled by the associated IA32_​MC7_​CTL (MSR 41Ch).

Implication: Due to this erratum, when IA32_​MC7_​CTL = 0h, the UCNA error may be logged but not signaled. When IA32_​MC7_​CTL =FFFFFFFFFh, the UCNA error may be logged and signaled, but may incorrectly set IA32_​MC7_​STATUS.EN (bit 60). Intel has not observed this erratum to affect any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR26. Errors May Occur During TOR CrashDump

Problem: When reading the TOR_​AUX array prior to a TOR CrashDump operation, a segment of the TOR_​AUX memory array may not be fully initialized, and the processor may return invalid data. As a result, a TOR_​AUX_​DATA_​PARITY_​ERR error may be logged (IA32_​MCi_​STATUS.MSCOD = 40h).

Implication: Due to this erratum, software analyzing a CrashDump record may not behave as expected.

Workaround: None identified. Software should ignore TOR_​AUX_​DATA_​PARITY_​ERR errors after a TOR CrashDump.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR27. TOR_​TIMEOUT May Occur Due to RID Values Outside Range Limit

Problem: When Integrity and Data Encryption (IDE) is enabled, Requestor ID (RID) values that falls outside the expected RID value limits defined by the Selective IDE RID Association 1 Register (Bits [23:8] in SIDERIDA1_​1, Bus: 29, 26, 4-1; Device: 9-2; Function: 0; Offset 324h) and Selective IDE RID Association 2 Register (Bits [23:8] in SIDERIDA2_​1, Bus: 29, 26, 4-1; Device: 9-2; Function: 0; Offset 328h) for the PCIe root port may lead to a TOR_​TIMEOUT Machine Check Exception reported in MC7_​STATUS (MSR 41Dh, MSCOD=0Ch), rather than a Completion Timeout.

Implication: Due to this erratum, a TOR_​TIMEOUT may occur, which may lead to a system hang.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR28. Removed

GNR29. RETRY_​RD_​ERR_​LOG_​MISC.DDR5_​9x4_​half_​device Bit May Be Incorrect

Problem: On systems using 9x4 DDR5 DIMMs, when Permanent Fault Detection (PFD) is disabled, the RETRY_​RD_​ERR_​LOG_​MISC.DDR5_​9x4_​half_​device bit (138_​MEM_​RRD + Offsets 22C54h, 22D80h, 2AC54h, 2AD80h, 22E60h, Bit 7) will always report 0 when an error is detected in device 8.

Implication: Due to this erratum, when an error is detected on device 8, the system software is not able to rely on the value of the RETRY_​RD_​ERR_​LOG_​MISC.DDR5_​9x4_​half_​device bit.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR30. Intel DSA Memory Write with Incorrect Parity May Result in a System Crash

Problem: When executing a copy operation, if an Intel DSA device receives a poisoned data response to a memory read request (Bus 8:11; Device: 1; Function: 0; Offset 104h, ERRUNCSTS.PTLP, bit[12]), an associated destination memory write with incorrect parity may be generated.

Implication: Due to this erratum, the memory write with incorrect parity may result in a machine check error leading to a system crash.

Workaround: None identified. It may be possible for the BIOS to contain a mitigation for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR31. Intel IAA Expand Operation With PRLE Format Input May Return an Error

Problem: Intel IAA Expand operation may parse beyond the required elements of Source 1 and return a Parquet Run Length Encoding (PRLE) Format Error (14h) unexpectedly.

Implication: Due to this erratum, software may receive a spurious error.

Workaround: None identified. Software should not send non-PRLE encoded stream data in Source 1.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR32. RDT MBA Cannot Throttle to Minimum Bandwidth

Problem: The system may not be limited to the minimum memory bandwidth possible when the maximum Intel® Resource Director Technology (RDT) Memory Bandwidth Allocation (MBA) delay value MSR throttle settings IA32_​L2_​QOS_​EXT_​BW_​THRTL_​[0..14] (at MSR address D50h...D5Eh) are configured by setting these registers to the maximum value of 90.

Implication: Due to this erratum, maximum bandwidth throttling cannot be guaranteed.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR33. APPP Error May Be Logged Incorrectly in Machine Check Status Register ADDRV

Problem: When the processor encounters an address parity error, it will signal an Address Parity Error (APPP) in [bit:58] of IA32_​MCi_​STATUS.ADDRV, the failing address in IA32_​MCi_​STATUS.ADDRV register may be incorrectly logged.

Implication: Due to this erratum, software that relies upon the IA32_​MCi_​ADDR.ADDR bits may not function as expected.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR34. Intel DSA Does Not Report IDPT Entry in SWERROR or Event Log

Problem: The Intel® Data Streaming Accelerator (DSA) device may not log the Inter-Doman Permissions Table (IDPT) entry number into the error information field of the SWERROR register or Event Log as defined by Intel® Data Streaming Accelerator Architecture Specification, document number 671116, when it attempts to update an IDPT entry that is inaccessible.

Implication: Due to this erratum, software that utilizes the Event Log or SWERROR register for debugging purposes may not be aware of the entry number that triggered this error. Intel has not observed any functional issues due to this erratum.

Workaround: None identified. Software can avoid this erratum by always providing a completion record for the Update Window descriptor.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR35. UBOXERRMISC_​CFG Registers Do Not Log Errors

Problem: The UBOXERR[MISC,MISC2, & MISC3]_​CFG registers (Bus: 30; Device: 0; Function: 0; Offset: [ECh,E8h, & F4h]) within the Ubox Event Control (EVNTS) PCI configuration space will not log errors and incorrectly read 0h unless written by software.

Implication: Due to this erratum, software that relies upon the UBOXERR[MISC,MISC2, & MISC3]_​CFG registers may function incorrectly.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR36. Intel DSA and Intel IAA Devices May Cause a Machine Check

Problem: Reads returning greater than 8 from some registers of Intel DSA and Intel IAA devices will result in a fatal Machine Check Exception (MCE) logged in MC4_​STATUS (MSR=419h, MSCOD=0000h, MCACOD=0x0E0Bh).

Implication: Due to this erratum, reads greater than 8 bytes will trigger a fatal MCE.

Workaround: None identified. Only software at the highest privilege level should access Intel DSA and Intel IAA devices.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR37. Intel DSA and Intel IAA Devices May Cause Invalid Translation Caching

Problem: Submitting a Disable Work Queue command to Intel DSA and Intel IAA devices does not drain in-flight address translations resulting in possible invalid translation caching, which may lead to an unpredictable system behavior.

Implication: Due to this erratum, Intel DSA and Intel IAA devices may not behave as expected.

Workaround: None identified. As a mitigation, software should replace the Disable Work Queue command with a Drain Work Queue command followed by a Reset Work Queue command.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR38. Incorrect FROM_​IP Value For an RTM Abort in BTM or BTS May be Observed

Problem: During RTM (Restricted Transactional Memory) operation when branch tracing is enabled using BTM (Branch Trace Message) or BTS (Branch Trace Store), the incorrect EIP value (From_​IP pointer) may be observed for an RTM abort.

Implication: Due to this erratum, the From_​IP pointer may be the same as that of the immediately preceding taken branch.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR39. Intel® PT Trace May Contain Incorrect Data When Configured With Single Range Output Larger Than 4 KB

Problem: Under complex micro-architectural conditions, when using Intel® Processor Trace (Intel® PT) with single range output larger than 4 KB, disabling Intel PT and then enabling Intel PT using the TraceEn bit in IA32_​RTIT_​CTL MSR (MSR 570h, bit 0) may cause incorrect output values to be recorded.

Implication: Due to this erratum, an Intel PT may contain incorrect values.

Workaround: None identified. Software should avoid using Intel PT Trace with single range output larger than 4 KB.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR40. S and AR Bits of MCi_​STATUS Registers Unexpectedly Cleared by UCNA or CE

Problem: An Uncorrected No Action (UCNA) or Correctable Error (CE) may incorrectly clear the Signaling (S; bit 56) or Action Required (AR; bit 55) flags of IA32.MCi_​STATUS registers.

Implication: Due to this erratum, software that relies on S and AR bits of IA32_​MCi_​STATUS registers may not function as expected.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR41. Completion Timeout When Using Link IDE And Selective IDE

Problem: When using both Link Integrity and Data Encryption (Link IDE) and Selective Integrity and Data Encryption (Selective IDE) capabilities for a PCIe port, the processor may respond with an incorrect StreamID field value in a completion packet.

Implication: Due to this erratum, an endpoint that relies upon coherent secure link StreamID field values when the Link IDE Stream State register (Bit [3:0]; Bus: 29, 28, 26, 5-1; Device: 9-2; Function: 0; offset 314h ) and the Selective IDE Stream State register (Bit [3:0], Bus: 29, 26, 4-1; Device: 9-2; Function: 0; offset 320h) are enabled may not function as expected and may lead to a device Completion Timeout (CTO) error.

Workaround: None identified. Software should not enable both Link IDE and Selective IDE for a PCIe port. See the Root Complex IDE Key Configuration Unit Software Programming Guide, document number 732838, for additional details.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR42. Mirrored 128b ECC Mode May Not Log DRAM Address With Poison

Problem: When a poison pattern error is detected with 128 bit Error Correcting Code (ECC) mode and Memory Mirroring mode enabled, the DRAM address may not be logged in RETRY_​RD_​ERR_​LOG (Bus:30; Device: 6-5; Function 6-1; Offset 2F10h + [0...3 × 4h]) register.

Implication: Due to this erratum, software that relies upon the RETRY_​RD_​ERR_​LOG register may not function as expected.

Workaround: A BIOS code change has been identified and may be implemented as a mitigation for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR43. Processor May Hang When AMX_​OPS_​RETIRED PMON Event is Counted

Problem: Under a complex set of microarchitectural conditions, when general performance counter IA32_​PMC0 (PERFCTR0 MSR C1h) is configured to count the AMX_​OPS_​RETIRED (Intel® Advanced Matrix Extensions [Intel® AMX]-centric) performance monitoring event (Event CEh, Any Umask), the processor may hang.

Implication: Due to this erratum, the processor may hang with an internal timeout error (MCACOD 0400h) logged into IA32_​MCi_​STATUS (MSR 40Dh).

Workaround: It may be possible for the BIOS to contain a mitigation for this erratum. This mitigation will result in the AMX_​OPS_​RETIRED events not counting. To measure the Intel® AMX utilization, software should use the AMX_​Busy metric featured by the Top-down Microarchitecture Analysis (TMA) method.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR44. Some PECI Wire Commands May Not be Serviced

Problem: Every 65536th transaction over the PECI wire that is not a Ping(), GetTemp(), or GetDIB() Service Command, may not be serviced.

Implication: Due to this erratum, the PECI wire may incorrectly continue to return an unexpected Completion Code (CC) of 83h after retrying for 850 ms and fail to return the read data or write the value.

Workaround: It may be possible to workaround this erratum with a PECI driver update.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR45. System Hang When Page Request Message Issued From Discrete Device

Problem: A Page Request Message with a Last Page In Group (LPIG) field value of 0 issued from a discrete PCIe device to the processor may behave unexpectedly.

Implication: Due to this erratum, the system may hang. Root complex integrated devices are not affected by this erratum.

Workaround: It may be possible for the BIOS to contain a mitigation for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR46. PLR and PEM PCS_​PSTATE Not Asserted or Incremented

Problem: The PCS_​PSTATE status (bit 29) in the Performance Limit Reasons (PLR) (Bus: 8; Device: 3; Function: 7; Offset: 12K+10×4×1-4d) and the Power and Performance Excursion Monitor (PEM) (Bus: 8; Device: 3; Function: 7; Offset: 44K+10×4×1-4d) will not be asserted when the Baseboard Management Controller (BMC) overrides the P-state and limits core frequency, and the PCS_​PSTATE counter (ID 29) in the PEM will not be incremented and will read 0.

Implication: Due to this erratum, software that relies upon the PCS_​PSTATE bits may behave unexpectedly.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR47. Invalid BMC Frame Data During Reset Cycling

Problem: The I3C_​MNG interface within the processor mistakenly uses a device's static address during AC reset cycling.

Implication: Due to this erratum, invalid BMC frame data or a GETPID command may cause the BMC to panic or crash, leading to a system hang.

Workaround: It may be possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR48. Unable to Access 32-bit Address MMIO Registers Out of Band

Problem: The processor logic incorrectly handles access requests from an out-of-band agent (such as BMC) to any MMIO registers with a 32-bit address.

Implication: Due to this erratum, out-of-band access to 32-bit address MMIO registers may result in a completion code of 90h (illegal command) with values of 0.

Workaround: It may be possible for the BIOS to contain a mitigation for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR49. PCIe TLP May be Lost After Link Down Event

Problem: If the first PCIe TLP received from the endpoint after a link down or hot-add event is a TLP with an LCRC error, one TLP may be lost on the link due to an incorrect Sequence Number in the NAK DLLP.

Implication: Due to this erratum, the system may log a Completion Timeout Status of 1 (ERRUNCSTS.CTE; Bus: 29, 28, 26, 5-1; Device: 9-2; Function: 0; Offset 104h; Bit 14) or Configuration Request Timeout of 1 (RPPIOSTS.CFGCTO; Bus: 29, 28, 26, 5-1; Device: 9-2; Function: 0; Offset 1ACh; Bit 2), leading to a device reset, a device (surprise) warm reset, or a failure to add the device.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR50. Intel IAA Decompression Logic May Return Incorrect Values in Completion Record When All Source 1 Data is Dropped

Problem: When an Intel® In-Memory Analytics Accelerator (Intel® IAA) device decompress operation has a non-zero Source 1 Size, and if the sum of Drop Initial Bits of Analytics Engine Configuration and State (AECS; offset 1DCh) and Ignore End Bits (Decompression Flags, bits [8:6]) is equal to Source 1 Size times 8, the operation correctly drops all the Source 1 data. However, if the operation also results in a recoverable output buffer overflow (Completion Record Status Code 0Bh), then the value of Bytes Completed in the Completion Record (bytes 4 to 7) or the value of Drop Initial Bits field in the AECS may be incorrect.

Implication: Due to this erratum, the incorrect values may lead to the subsequent decompress operation, that is, the continuation of the same job producing an incorrect result.

Workaround: None identified. Before submitting the descriptor, software can avoid this erratum by checking if the sum of Drop Initial Bits and Ignore End Bits equals Source 1 Size times 8. In this case, setting Source 1 Size, Drop Initial Bits, and Ignore End Bits all to 0 will produce the correct result.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR51. Remapping Hardware with Major Version Number 6 Incorrectly Advertises the ESRTPS Support

Problem: Remapping hardware Major Version Number 6 (VER_​REG.MAJOR_​VERSION_​NUMBER= 6, VTDBAR offset 0x0, bits 7:4) enables Enhanced Set Root Table Pointer Support (ESRTPS), but CAP_​REG.ESRTPS (VER_​REG.ESRTPS, VTDBAR offset 0x8, bit 63) is incorrectly reported as 0.

Implication: Due to this erratum, software may incorrectly determine the ESTRPS feature is not supported.

Workaround: None identified. System software can implement ESRTPS feature if VER_​REG.MAJOR_​VERSION_​NUMBER = 6.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR52. Reserved(0) Check For a PASID Table Entry May Not Happen For a DMA Request

Problem: When a DMA Operation encounters any Reserved(0) bits b[95:91] of a PASID table entry as incorrectly Set, the processor may fail to generate Intel VT-d fault SPT.3, may incorrectly generate Intel VT-d fault SPT.4, or fail to block the DMA request.

Implication: Due to this erratum, DMA Request may not behave as expected when encounter Reserved(0) of a PASID table. Intel has not observed this erratum with any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR53. Remapping Hardware Will Not Report The PASID Value For RTA.2 Faults in Modes Other Than Scalable Mode

Problem: When Remapping Hardware encounters RTA.2 fault condition in modes other than Scalable Mode (RTADDR.TTM==01), the Fault Recording Register (FRCDH_​REG_​0_​0_​0_​VTDBAR, offset 408h) will incorrectly report a value of 0 in the PASID Present (PP) field (bit 31) and in the PASID Value (PV) field (bits 59:40).

Implication: Due to this erratum, software can not rely on PASID value for RTA.2 faults in modes other than Scalable Mode. Intel has not observed this sighting/erratum to impact the operation of any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR54. Remapping Hardware Does Not Perform a Reserved(0) Check in Interrupt Remap Table Entry

Problem: Remapping hardware does not perform Reserved(0) check on b[127:HAW+64] of the Interrupt Remap Table Entry for a Posted Interrupt.

Implication: Due to this erratum, system software violating Intel VT-d architecture requirement by programming non-zero reserved values in b[127:HAW+64] of Interrupt Remap Table entry for Posted Interrupt may not fault on current processors but may fault on future processors. Intel has not observed this sighting/erratum with any commercially available system.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR55. Unexpected Recoveries With ASPM L1 in CXL Endpoint

Problem: When Compute Express Link (CXL*) ASPM (L1) entry flow is initiated, the CXL endpoint requests L1 for CXL.IO but not for CXL.CM, which may cause an extra Power Management (PM) REQ ACK.

Implication: Due to this erratum, the CXL endpoint may observe unexpected link recoveries.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR56. PCIe Infinite Recovery Loop During Link Equalization

Problem: When link equalization fails at Gen5 or Gen4, and the endpoint disables that rate, the processor may unexpectedly attempt to recover at the link partner's advertised speed resulting in an infinite recovery loop.

Implication: Due to this erratum, the PCIe link may fail to train, preventing DL-Init, which causes the Data Link Layer Link Active (DLLLA, bit 13) in Link Status (LINKSTS, offset 52h) to remain unset.

Workaround: None identified. To mitigate this erratum, disable Gen5 or Gen4 per affected port to train at Gen4 or Gen3 within BIOS by using the Requested Link Speed setting.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR57. Incorrect B2CMI MCi_​STATUS_​SHADOW.CORRCOUNT Value

Problem: During memory mirror failover, the value in Bridge to Converged Memory Interface (B2CMI) MCi_​STATUS_​SHADOW.CORRCOUNT Offset 1C0h (bits 52:38) may not match the CORRECTED_​ERROR_​COUNT register values in IA32_​MCi_​STATUS (bits 52:38).

Implication: When this erratum occurs, software that relies upon the B2CMI MCi_​STATUS_​SHADOW.CORRCOUNT register may not function correctly.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR58. Boot Failure During BIOS Update With Missing CHA RTID Table

Problem: A Global Reset following an early warm reset during a BIOS update may fail to clear the CPLD SRAM on the non-legacy socket prior to ISCLK provisioning and may result in the CPLD becoming unsynchronized.

Implication: Due to this erratum, a boot failure may occur, resulting in a missing CHA Request Transaction ID (RTID) table in the crashdump.

Workaround: It may be possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR59. Incorrect RAPL PPL1 Limit

Problem: Platform Running Average Power Limit (RAPL) Platform Power Limit1 (PPL1) is clipped, resulting in the value of MAX_​PPL2 (bits 48:32; Offset 665h) being used instead of MAX_​PPL1 (bits 16:0; Offset 665h).

Implication: Due to this erratum, the maximum value of PPL2 may restrict PPL1, leading to an incorrect RAPL.

Workaround: It may be possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR60. Incorrect Values For CHA ALL0 And CHA ALL1

Problem: For Out-of-Band access, the BDFs for (CHA ALL0 Bus 31; Device 14-0; Function 7-0) and (CHA ALL1 Bus 30; Device 28-14; Function 7-0) PCI Configuration Space Registers are incorrectly mapped.

Implication: Due to this erratum, the BMC that relies upon the values in CHA ALL0 or CHA ALL1 may function incorrectly.

Workaround: None identified. To access the CHA ALL0 PCI Configuration Space Register, the BMC needs to use (Bus 30; Device 28-14; Function 7-0). Additionally, to access the CHA ALL1 PCI Configuration Space Register, the BMC needs to use (Bus 31; Device 14-0; Function 7-0).

Status: For the steppings affected, see the Summary Tables of Changes.

GNR61. Internal Timer Machine Check Error May Cause System Hang

Problem: Under complex microarchitectural conditions, an internal timer Machine Check Error (MSCOD E1CDH, MCACOD 0x400h) may occur when executing Advanced Matrix Extension (AMX) instructions under stress.

Implication: When this erratum occurs, the system may hang.

Workaround: It may be possible for BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR62. REP SCASB or REP CMPSB Instructions May Return Incorrect Results

Problem: When software executes Repeat Scan String Byte (REP SCASB) or Repeat Compare String Byte (REP CMPSB) instructions on a core, another core or thread may modify the memory being accessed.

Implication: Due to this erratum, the SCASB or the CMPSB instruction may return incorrect results.

Workaround: It may be possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR63. System Hang During Sideband and Traffic To B2CXL

Problem: During the transmission of sideband traffic (both posted and non-posted) to the Bridge to CXL (B2CXL) sideband endpoint, the Intel On-Chip System Fabric - Side Band (IOSF-SB) endpoint may experience stalling due to the IP agent logic lacking an additional check for processing new back-to-back messages.

Implication: Due to this erratum, the system may hang.

Workaround: It may be possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR64. SYS_​RESET_​N Trigger May Lead to MCA_​GPSB_​TIMEOUT

Problem: When the SYS_​RESET_​N pin is triggered before the reset flow phase 5 completes, an unexpected microcode timeout may occur.

Implication: Due to this erratum, the system may hang with MCA_​GPSB_​TIMEOUT (IA32_​MCi_​STATUS.MCACOD=402h and IA32_​MCi_​STATUS.MSCOD=0B00hh).

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR65. Intel® OOBM Services Module RDIAMSREX Command Unable to Access MSRs Under IERR Conditions

Problem: Under an IERR condition, the Intel® Out-of-Band Management Services Module (Intel® OOBM Services Module) RDIAMSREX command is unable to access Model Specific Registers (MSRs) and will return a completion code of 93h.

Implication: Due to this erratum, software that relies on the RDIAMSREX command under IERR conditions may not behave as expected. The RDIAMSR command is not impacted by this erratum.

Workaround: It may be possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR66. CXL Mode Incorrectly Identifies ASPM L1 Aborts

Problem: In the Compute Express Link* (CXL*) mode, the processor may incorrectly identify Active State Power Management (ASPM) L1 aborts as errors when the ARBMUX requests L1 and transitions to an active state before the LTSSM reaches L1, resulting in IBSTERRRCRVSTS.RECOVCNT (bits 30:16; Offset 4E4h) overcounting.

Implication: Due to this erratum, software that relies upon the IBSTERRRCRVSTS.RECOVCNT bits may not function as expected.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR67. PCIe Root Port May Not Reduce Link Width

Problem: During a PCIe Link Width Degrade event on PCIe devices, the root port may not successfully transition to a reduced link width due to a timeout in the PCIe Configuration.Linkwidth.Accept to Configuration.Lanenum.Wait state.

Implication: Due to this erratum, the PCIe root port may encounter unexpected recoveries, unexpected link width degrade attempts, uncorrectable errors, Surprise Link Down, and LTSSM errors.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR68. Intel® PT Incorrect CR3-Filtering

Problem: When the Intel® Processor Trace (Intel® PT) CR3-filtering mechanism is enabled using the CR3Filter bit in IA32_​RTIT_​CTL MSR (MSR 570h, bit 7), CR3 control register bits [63:52] are not compared with the IA32_​RTIT_​CR3_​MATCH MSR (MSR 572h) value.

Implication: Due to this erratum, software that relies upon the IA32_​RTIT_​CTL MSR (bit 7) may function incorrectly.

Workaround: None identified. Software may mitigate this erratum by copying the CR3 register value into IA32_​RTIT_​CR3_​MATCH MSR.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR69. Address May Not be Logged For a UCR Error Detected in The MLC

Problem: An Uncorrected No Action Required (UCNA) error logged in machine check bank 3 with MC3_​STATUS.MCACOD=0179h (MSR 40Dh, bits [15:0] may not include a valid address in MC3_​ADDR (MSR 40Eh) when an ECC Uncorrected Recoverable (UCR) error is detected on an Mid-Level Cache (MLC) eviction.

Implication: Due to this erratum, software may not have access to the address of the poisoned data produced by the ECC UCR error in the MLC.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR70. Incorrect Last Branch From Value in BTS Branch Record During a Task Switch

Problem: When branch tracing is enabled using Branch Trace Store (BTS) during a task switch, the processor reports the linear address of the branch target in the branch record field "Last Branch from" instead of the linear address of the instruction from which branch was taken.

Implication: Due to this erratum, debug tools relying on BTS may misinterpret control flow.

Workaround: None identified. Software should avoid using BTS to determine the accuracy of branch prediction.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR71. VMREAD/VMWRITE Instructions May Not Fail When Accessing an Unsupported Field in VMCS

Problem: The execution of VMREAD or VMWRITE instructions should fail if the value of the instruction's register source operand corresponds to an unsupported field in the Virtual Machine Control Structure (VMCS). The correct operation is that the logical processor will set the Zero Flag (ZF), write 0CH into the VM-instruction error field and for VMREAD leave the instruction's destination unmodified.

Implication: Due to this erratum, the instruction may instead clear the ZF, leave the VM-instruction error field unmodified, and, for VMREAD, modify the contents of its destination. Accessing an unsupported field in VMCS may fail to properly report an error. In addition, a VMREAD from an unsupported VMCS field may unexpectedly change its destination. Intel has not observed this erratum with any commercially available software.

Workaround: None identified. Software should avoid accessing unsupported fields in a VMCS.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR72. PMON Unit Control Unfreeze May Cause COUNTERVALUE Registers to Overcount

Problem: When the PMON Unit Control (PMONUNITCTRL) FREEZECOUNTERS (Offset: 2800h; Bit: 0) is set to 0 while the PMON GLOBALPMONFREEZE register is set to 1, the unit control may unexpectedly override the global control and unfreeze the PMONCNTR_​0,1,2,3,4 COUNTERVALUE (Offsets 2808h, 2810h, 2818h, 2820h, 2828h; Bits: [47:0]).

Implication: Due to this erratum, software that relies on the value of COUNTERVALUE may observe higher than expected values.

Workaround: None identified. The software should use only the unit control unfreeze when the global control freeze is set to 0.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR73. HPR_​CAUSE0 Not Cleared With a Global Reset or Wake Event

Problem: When a global reset or wake from an Sx state occurs, HPR_​CAUSE0 register (Offset: 192Ch) is not cleared.

Implication: Due to this erratum, software that relies on the HPR_​CAUSE0 register may function incorrectly.

Workaround: It may be possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR74. Performance Monitoring Event MEMORY_​ACTIVITY.STALLS_​L2_​MISS May Undercount

Problem: The performance monitoring event MEMORY_​ACTIVITY.STALLS_​L2_​MISS (Event 47h, UMASK 05h) may undercount for cases of streaming partial loads.

Implication: Due to this erratum, performance monitoring counters may undercount values for this event and the Top-down Microarchitecture Analysis (TMA) L2_​Bound may be over-estimated for streaming partial loads.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR75. System Reset May Incorrectly Overwrite Previous Crashlog

Problem: When the ENABLETRIGGERONCE bit is set to '1' (CRASHLOG_​CTRL Bus 8; Device 3; Function 0; Offset 1B8h; bit [6] or MSM_​BIOS_​CRASHCONTROL Bus 8; Device 3; Function 0; Offset 158h; bit [6]) and a crashlog is triggered on a system reset, an additional crashlog may be incorrectly triggered on a subsequent system reset prior to the CRASHLOG_​CTRL.REARMTRIGGER or MSM_​BIOS_​CRASHCONTROL.REARMTRIGGER bits being set to '1'.

Implication: As a result of this erratum, data collected during a previous crashlog reporting may be overwritten.

Workaround: It may be possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

GNR76. Instruction Timeout VM Exit Will Not Set Guest RFLAGS.RF During #UD

Problem: When the VM-Execution Control "Instruction timeout" (bit 31) is set to 1, and a VM exit occurs with basic exit reason 75 (instruction timeout) during the delivery of an invalid opcode (#UD) exception, the processor will not set Guest RFLAGS.RF (bit 16).

Implication: Due to this erratum, when the VMM resumes the guest at the same instruction, and an instruction breakpoint is set in the guest, it may trigger double instruction breakpoints (#DB).

Workaround: A mitigation for this erratum is for VMMs to set guest RFLAGS.RF before resuming guest execution following an instruction timeout VM exit.

Status: For the steppings affected, see the Summary Tables of Changes.