Intel® 700 Series Chipset Family On-Package Platform Controller Hub (PCH)
Datasheet, Volume 1 of 2
Supporting Raptor Lake - PX Platforms
PCI Express* Port Support Feature Details
| PCIe Controller Feature | Gen1 | Gen2 | Gen3 |
|---|---|---|---|
| L1 Sub-States (L1.0, L1.1, L1.2) | Yes | Yes | Yes |
| RX/TX L0s Link State | Yes | Yes | Yes |
| S3/S4/S5 Sleep States (Sx) | Yes | Yes | Yes |
| Common Clock Mode | Yes | Yes | Yes |
| Separate Reference Clock with Independent SSC (SRIS) | Yes | Yes | Yes |
| Separate Reference Clock with No SSC (SRNS) | Yes | Yes | Yes |
| Precision Time Management (PTM) | Yes | Yes | Yes |
| Advanced Error Reporting (AER) | Yes | Yes | Yes |
| End-to-End Lane Reversal | Yes | Yes | Yes |
| Latency Tolerance Reporting (LTR) | Yes | Yes | Yes |
| PCIe TX Half Swing | No | No | No |
| PCIe TX Full Swing | Yes | Yes | Yes |
| Run Time D3 (RTD3) | Yes | Yes | Yes |
| Access Control Services (ACS) | Yes | Yes | Yes |
| Alternative Routing-ID Interpretation (ARI) | Yes | Yes | Yes |
| Dynamic Link Throttling | Yes | Yes | Yes |
| Port 80h Decode | Yes | Yes | Yes |
| Lane Polarity Inversion | Yes | Yes | Yes |
| PCIe Controller Root Port -> Hot-Plug | Yes | Yes | Yes |
| Downstream Port Containment (DPC) | Yes | Yes | Yes |
| Enhanced Downstream Port Containment (eDPC) | No | No | No |
| Virtual Channel (VC)[7:0] | VC0 | VC0 | VC0 |
| NVMe Cycle Router | No | No | No |
| Volume Management Device (Intel® VMD) | Yes | Yes | Yes |
| Hybrid Dual Port Module Support (M.2 2px2) | Yes | Yes | Yes |
| Peer-2-Peer (P2P) Mem Write Transactions | No | No | No |
| Peer-2-Peer (P2P) Mem Read Transactions | No | No | No |
| Peer-2-Peer (P2P) MCTP VDM Transactions | Yes | Yes | Yes |
PX PCH Supported PCI Express* Link Configurations
- The PCH PCIe* Link Configuration support will vary depending on the PCH SKU. Refer to the PCH SKU details covered in the "Introduction" section
- RP# refers to a specific PCH PCI Express* Root Port #; for example RP3 = PCH PCI Express* Root Port 3
- A PCIe* Lane is composed of a single pair of Transmit (TX) and Receive (RX) differential pairs, for a total of four data wires per PCIe* Lane (such as, PCIE[3]_TXP/ PCIE[3]_TXN and PCIE[3]_RXP/ PCIE[3]_RXN make up PCIe Lane 3). A connection between two PCIe* devices is known as a PCIe* Link, and is built up from a collection of one or more PCIe* Lanes which make up the width of the link (such as bundling 2 PCIe* Lanes together would make a x2 PCIe* Link). A PCIe* Link is addressed by the lowest number PCIe* Lane it connects to and is known as the PCIe* Root Port (such as a x2 PCIe* Link connected to PCIe* Lanes 3 and 4 would be called x2 PCIe* Root Port 3).
- The PCIe* Lanes can be configured independently from one another but the max number of configured Root Ports (Devices) must not be exceeded
- Unidentified lanes within a PCIe* Link Configuration are disabled but their physical lanes are used for the identified Root Port
- Lane Reversal Supported Motherboard PCIe* Configurations = 1x4, 2x1+1x2, and 2x2
- For unused USB 3.2/PCIe* Combo Lanes, the unused lanes must be statically assigned to PCIe* or USB 3.2 via the USB 3.2/PCIe* Combo Port Soft Straps discussed in the SPI Programming Guide and through the Intel® Flash Image Tool (Intel® FIT) tool.