Problem

If a PCH USB Type-C* port is configured in Device Mode (or in DbC mode) and connected to an external USB 3.2 host controller, it may cause the USB port to go into a non-functional state in the following scenarios: 1. The PCH resumes from S3, S4, or S5 state, the port may remain in U2. 2. The port is connected to a USB 3.2 Gen 1x1 host controller when resuming from S3, S4, S5, or G3, the port may enter into Compliance Mode or an inactive state if Compliance Mode is disabled. 3. The port is connected to a USB 3.2 Gen 2x1 host controller when resuming from S3, S4, S5, or G3, the port may enter an inactive state.

Implication

PCH USB Type-C port configured in Device Mode (or in DbC mode) may fail to enumerate or become unavailable.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI implements the Power Management Link Timer (PM LC Timer) Timeout value as 10 us instead of 4 us as defined by the USB 3.2 specification.

Implication

USB-IF xHCI CV TD 7.21 may report a failure. Intel has obtained a waiver for TD 7.21. Note: No functional issues are expected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the xHCI controller is stressed with concurrent traffic across multiple USB ports, the xHCI controller may fail to service USB 2.0 Isochronous IN endpoints within the required service interval.

Implication

USB 2.0 isochronous devices connected to the xHCI controller may experience dropped packets.Note: This issue has only been observed in a synthetic environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

For flash device suspend / resume opcodes, the SPI controller does not use JEDEC SFDP's 13th DWORD bits [15:0], Program Suspend Instruction and Program Resume Instruction fields. The controller only uses bits [31:16], Suspend Instruction and Resume Instruction fields, to obtain the suspend / resume opcodes.

Implication

If the SPI flash requires bits [15:0] to be different than bits [31:16], then the suspend / resume feature is not functional. In this case, system behavior varies depending on what the suspend / resume instruction is and when it is generated.Note: major flash vendors have been using the same value for bits [31:16] and bits [15:0].

Workaround

None identified.If a device requires bits [15:0] to be different than bits [31:16], then disable the device suspend / resume via the SPI Suspend / Resume Enable soft strap.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The Intel Trace Hub Pipe Line Empty bit (CSR_​MTB_​BAR, Offset 0xD4) for a given output port may be set while the Input Buffer Empty for the associated output port is not set. This will only happen when the captureDone signal is de-asserted by clearing the ForceCaptureDone bit (CSR_​MTB_​BAR, Offset 0xD8) is cleared or the StoreQual[0] signal is de-asserted by the Trigger Unit before the pipe line is empty, and the destination is either system memory or USB (DCI).

Implication

There may be valid trace data in the trace source input buffer which did not get sent to the destination (output port).

Workaround

None identified. CaptureDone should be cleared or de-asserted after the pipe line is empty.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI may generate an unexpected short packet event for the last transfer's Transfer Request Block (TRB) when using Non-Event Data TRB with multiples TRBs.

Implication

Transfer may fail due to the packet size error.

Workaround

None identified.

Intel recommends software to use Data Event TRBs for short packet completion.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The IOSF-SB eSPI Link Configuration Lock (SBLCL) bit (offset 4000h, bit 27 in eSPI PCR space) is reset by RSMRST# assertion instead of PLTRST# assertion.

Implication

If the SBLCL bit is set to 1, software will not be able to access the eSPI device Capabilities and Configuration register in the reserved address range (0h - 7FFh) until RSMRST# asserts.

Workaround

If software needs to access the eSPI device reserved range 0h - 7FFh while SBLCL bit is set to 1, a RSMRST# assertion should be performed.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If USB audio offload is enabled for a USB Full-Speed Isochronous audio device connected behind a USB 2.0 or later hub and there is an active concurrent bulk transfer to another device on any port of the xHCI controller or behind the hub, the controller may stall the offloaded audio traffic and a split transaction error may occur.

Implication

The USB audio offload playback may stop. Audio may be recovered if the audio stream is paused and restarted, the audio device is removed and reconnected, or the audio application is restarted.

Workaround

None identified. A mitigation for this erratum is available with Intel^® Smart Sound Technology version 10.29.00.5574 or later for systems with Microsoft Windows* 11 OS Release or Intel Smart Sound Technology version 10.29.00.7767 or later for systems with Microsoft Windows 10 OS Release. This mitigation will disable audio offload functionality for USB audio devices connected behind a hub.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Upon GbE controller D3 exit, the GbE host driver performs a controller reset. During this reset, software accesses to the GbE MMIO registers may not complete.

Implication

The system may hang.Note: This erratum has only been observed in a synthetic environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI spec version 1.2 defines the PCI Express Capability structure offset 04h Device Capabilities (DVSEC) field to be 8 bytes. The USB Virtualization Based Trusted IO (VTIO) Management controller implements the DVSEC field as 12 bytes.

Implication

An USB controller driver may not be able to enable the USB VTIO controller.

Workaround

None identified. To mitigate this erratum, an Independent Software Vendor could account for the field length in the USB controller driver.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Setting the Disable SLP_​X Stretching After SUS Well Power Up (DIS_​SLP_​X_​STRCH_​SUS_​UP) bit (offset 1020h, bit 12 in PMC_​MMIO space) to 1 does not disable the SLP_​A# Minimum Assertion Width (SLP_​A_​MIN_​ASST_​WDTH) timer (offset 1020h, bit 17 and 16 in PMC_​MMIO space).

Implication

G3 exit duration may be extended by the value programmed in the SLP_​A_​MIN_​ASST_​WDTH register.

Workaround

None identified. To mitigate the issue for platforms that do not require SLP_​A# stretching, BIOS should program SLP_​A_​MIN_​ASST_​WDTH to 0.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller does not return the correct completion code for the Force Header Command as defined in the Section 4.6.16 of the eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Requirements Specification Rev 1.2.

Implication

xHCI CV TD4.12 - Force Header Command Test may report an error. Intel has obtained a waiver for TD 4.12. The Force Header Command is only used by the USB-IF Command Verifier (xHCI CV) tool for device testing. There are no known functional failures due to this erratum.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On USB 3.2 Gen 1x1 only capable ports, including ports configured as USB 3.2 Gen 1x1 by soft strap, the xHCI controller may send only 15 LFPS signals instead of a burst of 16 LFPS signals as specified by the USB 3.2 specification.

Implication

There are no known functional implications due to this erratum. LFPS handshake requires the receiver link partner to only detect 2 LFPS signals. This issue may impact the SuperSpeed compliance test case which checks for the 16 LFPS burst requirements: TD6.4, TD6.5, and TD7.31.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

During the hot-plug of a USB 2.0 hub with Low-Speed or Full-Speed device connected behind the hub, a split transaction error may occur during the enumeration of the USB Low-Speed or Full-Speed device.

Implication

Due to this erratum, the USB Low-Speed or Full-Speed device may fail to enumerate when connected to the USB 2.0 hub. This condition is recovered after the xHCI controller has been reset (for example, software setting the xHCI Host Controller Reset (HCRST) bit or by performing a power button override).

Workaround

A fix for this erratum is available in BIOS. Please see BIOS version 3342_​00 release or later.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A delay in the availability of LCRD1 (Link Credit 1) from a USB 3.2 hub, with two or more downstream USB 3.2 bulk endpoint devices engaged in SuperSpeedPlus concurrent transfers, may lead to the connected xHCI controller sending the ACK and Status of a transfer packet out of order.

Implication

Due to this erratum, a USB 3.2 bulk endpoint device may not respond to subsequent transfers. It may be possible for a device driver to recover the USB 3.2 device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the I2S interface is in device mode, the audio controller may not be correctly configured if the audio codec requires high frame polarity.

Implication

Due to this erratum, the left and right audio channels may swap when frame polarity is set to high.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The USB 3.2 Debug Class Device (DbC) reports an incorrect Sublink Speed Attribute ID (SSID) value in the SuperSpeedPlus USB Device Capability field.

Implication

Due to this erratum, the PCH USB 3.2.DbC (Debug Capability) device may fail to enumerate when connected to a USB 3.2 Gen 2x1 port.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When multiple USB 2.0 split transaction errors occur, the xHCI host controller may become unresponsive.

Implication

Due to this erratum, USB devices connected to the xHCI controller may not function.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On systems with dual IO mode enabled, SPI0_​IO2 and SPI0_​IO3 may momentarily drive low before these signals are pulled high by internal resistors during boot from the G3 state.

Implication

Due to this erratum, unexpected system behavior may occur on systems when SPI0_​IO2 and SPI0_​IO3 signals are connected to an SPI device.

Workaround

None identified. To mitigate this erratum, do not connect SPI0_​IO2 and SPI0_​IO3 to an SPI device in SPI0 dual IO mode enabled systems.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When doing a hotplug on a USB hub with two or more USB Full-speed or Low-speed devices each with a 1 ms service interval interrupt endpoint, a race condition may occur between the PMC and the xHCI controller.

Implication

The processor may fail to enter C3 or deeper package C-States. Note: This erratum has only been observed in a synthetic environment.

Workaround

None identified. This condition is recovered after the xHCI controller has successfully entered D3.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller may fail to handle a zero-length data packet when doing concurrent traffic with the following devices connected on three separate root ports:

- USB 3.2 Gen 2x1 (or 2x2) hub with at least two USB 3.2 bulk devices.

- USB 3.2 Gen 2x1 (or 2x2) hub with at least two USB 3.2 bulk devices.

- USB isochronous device that sends zero-length data packets.

Implication

Due to this erratum, the xHCI controller may hang. Intel has only observed this behavior with USB audio offload enabled and USB 2.0 audio devices that send zero-length data packets.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a Timed GPIO event is counted in the Event Counter Capture (TGPIOECCV) register (offset 1238h, bits 31 to 0 in PWRMBASE space), the Time Capture (TGPIOTCV) register (offset 1230h, bits 31 to 0 in PWRMBASE space) value is not immediately updated after that event is counted.

Implication

A Timed GPIO event may have a mismatched time stamp.

Workaround

None identified. A Timed GPIO driver can partially mitigate for this erratum by detecting that a TGPIOECCV register change has occurred without a TGPIOTCV register change and then repeatedly re-read the TGPIOTCV register until a change does occur.

Status

For the steppings affected, refer to the Summary Table of Changes.