13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
764981 | 07/13/2023 | Public |
ATS Control (ATS_CTRL_0_2_0_PCI) – Offset 206
ATS Control register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0x0 | RW | ATS Enable (AE) When Set, the function is enabled to cache translations. Processor graphics ignores this field, as GT uses GTLB as IOTLB and only pretends to software that it has a Device-TLB. Software is expected to Set this field before configuring extended context-entry for Device2 with Page Request Enable field Set. For compatibility, this field is implemented as RW as software can read it to determine ATS enable status. |
14:5 | 0x0 | RSV | RESERVED (Reserved_0) The field 'Reserved' in register 'ATS Control' does not have a description in the BXML |
4:0 | 0x0 | RW | Smallest Translation Unit (STU) This value indicates to the Endpoint the minimum number of 4096-byte blocks that is indicated in a Translation Completion or Invalidate Request. This is a power of 2 multiple and the number of blocks is 2^STU. A value of 0 indicates one block and value 1F indicates 2^31 blocks. For IGD this must be programmed to 0h for 4KB as smallest translation unit. |