13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2
XHCI Aux Clock Control Register (XHCI_AUX_CCR) – Offset 816C
XHCI Aux Clock Control Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:20 | 0x0 | RO | Reserved (RSVD) Reserved |
19 | 0x1 | RW | USB3 Partition Engine/Link trunk gating Enable (PARUSB3_ENG_GEN) When set to 1 enables gating of the SOSC trunk to the XHCI engine and link in the PARUSB3 partition. |
18 | 0x1 | RW | USB3 Partition Frame Timer trunk gating Enable (PARUSB3_LINK_GEN) When set to 1 enables gating of the SOSC trunk to the Frame timer in the PARUSB3 partition. |
17 | 0x1 | RW | USB2 link partition clock gating enable (PARUSB2_CLK_GEN) When set to 1 enables gating of the SOSC trunk to the USB2 link and Phy logic in the PARUSB2 partition. |
16 | 0x1 | RW | USB2/USHIP 12.5 MHz partition clock gating enable (USHIP_PCGEN) When set to 1 enables gating of the 12.5 MHz SOSC trunk to the USB2 and USHIP logic in the PARUSB2 partition. |
15 | 0x0 | RO | Reserved1 (RSVD1) Reserved |
14 | 0x1 | RW | USB3 Port Aux/Core clock gating enable (USB3_AC_CGE) When set, allows the aux_cclk clock into the USB3 port to be gated when conditions are met. |
13:12 | 0x0 | RW | Rx Detect Timer when port Aux Clock is Gated (RX_DT_ACG) This field defines the value of the timer used to perform Rx Detect when port Aux Clock has been gated. |
11:10 | 0x0 | RW | Reserved2 (RSVD2) Reserved |
9 | 0x0 | RW | Aux Clock Gating Counter PipeStage Enable (AUXCLKGT_CNTEN_PIPE_STGEN) Policy to enable pipe stage on cnten of aux_clk and frame_clk gating logic |
8 | 0x0 | RW | Reserved3 (RSVD3) Reserved |
7 | 0x0 | RW | Frame Timer Clock Gating Ports in U2 Enable (FTCGPU2E) This bit, when set, allows Host Controller to gate the clock to the Frame Timer when ports are in U2. |
6 | 0x0 | RW | USB2 port clock throttle enable (USB2_PC_TE) When set, allows the Aux clock into the USB2 ports to be throttled when conditions allow. |
5 | 0x1 | RW | XHCI Engine Aux clock gating enable (XHCI_AC_GE) When set, allows the aux clock into the XHCI engine to be gated when idle. |
4 | 0x1 | RW | XHCI Aux PM block clock gating enable (XHCI_APMB_CGE) When set, allows the aux clock into the Aux PM block to be gated when idle. |
3 | 0x1 | RW | USB3 Aux Clock Trunk Gating Enable (USB3_AC_TGE) When set, allows Aux Clock Trunk feeding to USB3.0 ports to be gated when port Aux clock is gated at all USB3.0 ports and all USB3.0 modPHY instances. |
2 | 0x1 | RW | USB3 Port Aux/Port clock gating enable (USB3_AP_CGE) When set, allows the aux_pclk clock into the USB3 port to be gated when conditions are met. |
1 | 0x0 | RW | ModPHY port Aux clock gating enable in U2 (MPP_AC_GEU2) When set, allows the aux clock into the ModPhy to be gated when Link is in U2 and pipe has been in PS3 for at least the time defined by U2 Residency Before ModPHY Clock Gating field. |
0 | 0x0 | RW | ModPHY port Aux clock gating enable in Disconnected, U3 or Disabled (MPP_AC_GE_DDU3) When set, allows the aux clock into the ModPHY to be gated when Link is in Disconnected, U3 or Disabled state. |