Channel Configuration (CCFG) – Offset D0 - 1.3 - ID:764981 | 13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

ID	Date	Version	Classification
764981	07/13/2023		Public

Channel Configuration (CCFG) – Offset D0

Channel Configuration

Bit Range	Default	Access	Field Name and Description
31	0x0	RW/L	Config Receive Enabled (CRE) When set, enables receiving upstream configuration cycles which are normally not allowed. These may be peer cycles or sent to DMI depending upon the result of peer decode. When cleared, upstream configuration cycles will be completed with Unsupported Request completion status. This register is Read-Only if LPCR.SRL field is set.
30	0x0	RW/L	I/O Receive Enabled (IORE) When set, enables receiving upstream IO cycles which are normally not allowed. These may be peer cycles or sent to DMI depending upon the result of peer decode. When cleared, upstream I/O cycles will be completed with Unsupported Request completion status. This register is Read-Only if LPCR.SRL field is set.
29	0h	RO	Reserved
28	0x0	RW	Upstream Fabric Decode Mode (UFDM) When is cleared, DMI would send all Upstream transactions using Implicit Decode except for NVMe peer usages which would use Fabric Decode. When is set, DMI will force all Upstream transactions to use Fabric Decode.
27	0x1	RW	Upstream Atomic Request Peer Disable (UARPD) When set, Upstream Atomic Request will be forwarded to fabric using implicit decode, bypassing the peer decode phase. This results in shorter Atomic latency to memory. When clear, Upstream Atomic Request will be forwarded to fabric using fabric decode, unless specifically called out otherwise. This bit can only be set if the platform does not support peer-to-peer atomic request.
26	0x1	RW	Upstream Memory Read Peer Disable (UMRPD) When set, upstream memory reads will be forwarded to fabric using implicit decode, bypassing the peer decode phase. This results in shorter memory read latency to memory. When clear, upstream memory reads will be forwarded to fabric using fabric decode, unless specifically called out otherwise. This bit can only be set if the platform does not support peer-to-peer memory reads.
25	0x1	RW	Upstream Posted Memory Write Peer Disable (UPMWPD) When set, upstream posted memory writes will be forwarded to fabric using implicit decode, bypassing the peer decode phase. This results in shorter memory write latency to memory. When clear, upstream posted memory writes will be forwarded to fabric using fabric decode, unless specifically called out otherwise. This bit can only be set if the platform does not support peer-to-peer memory writes. Upstream messages, such as MCTP are not subjected to this bit.
24	0x1	RW	Upstream Posted Split Disable (UPSD) When '0', upstream posted memory requests will be split on boundaries defined by the UPRS bit in this register. When '1' (default), upstream posted memory requests will not be split and will be presented to the backbone as received from the link. This register has no effect on posted messages which are never split. Note: This register is per-port. Software can independently enable or disable splitting for each ports.
23	0x0	RW	Upstream Non-Posted Split Disable (UNSD) When '0', upstream non-posted requests will be split on boundaries defined by the UNRS bit in this register. When '1', upstream non-posted requests will not be split and will be presented to the backbone as received from the link. If configured not to split, the NPAP bit in this register must be set to '1' (never pre-allocate). Note: This register is per-port. Software can independently enable or disable splitting for each ports.
22:17	0x0	RW	Non-Posted Pre-Allocation Size (NPAS) This value is used when the NPAP in this register is set to 1. This field reserves the buffers in the Transmit Completion Queue based on the value programmed in this register. 000000: Completion Buffer size matching Credit advertised on IOSF Primary 000001: 256B (1 x 256B) 000010: 512B (2 x 256B) .... Note: Software must ensure this register must not be programmed to a value more than the Transmit Completion Command Queue.
16	0x0	RW	Non-Posted Pre-Allocation Policy (NPAP) Indicates whether pre-allocation of the shared resource should be performed. Valid encodings are: Bits Description 0 Always Pre-allocate 1 Never Pre-Allocate Note: This register is per-port. Software can independently enable or disable splitting for each ports.
15	0x0	RW	Dynamic Clock Gating Enable on ISM Active (DCGEISMA) 0: Shared resource dynamic clock gating is allowed when ISM is not in Idle state. 1: Shared resource dynamic clock gating is only allowed when ISM is in Idle state. Note: Only Port 1 register is used. This is a per controller register.
14	0h	RO	Reserved
13:12	0x0	RW	Upstream Non-Posted Request Delay (UNRD) Sets the minimum delay between back-2-back non-posted read request puts on the IOSF backbone. The delay value is in 125 MHz backbone command clocks. Valid encodings are: Bits Clock Delay 00 0 clocks 01 4 clocks 10 8 clocks 11 16 clocks
11	0x0	RW	Retry Buffers Minimum Size (RBMS) When '0', retry buffer is sized according to port configuration: See Queue size table for queue sizes based on port configuration. When '1', the retry command buffer is sized at minimum 1 cmd. This bit has no impact on data buffer sizing. This field can be modified only when the Link has been disabled LCTL.LD=1.
10	0h	RO	Reserved
9	0x0	RW	Minimum Receive Non-Posted Credits (MRNPC) When set, allows only the minimum number of PCI Express receive credits for non-posted requests for this VC. For this to take effect, the Link Disable must be set. Bits Description 0 Full credits based on configuration. 1 Minimum number of credits advertised (independent of configuration). 1 non-posted header, 1DW non-posted data Note: PCI Express Completion receive credits are always infinite.
8	0x0	RW	Minimum Receive Posted Credits (MRPC) When set, allows only the minimum number of PCI Express receive credits for posted requests for this VC. For this to take effect the Link Disable must be set. Bits Description 0 Full credits advertised based on configuration 1 Minimum number of credits advertised (independent of configuration): 1 posted header, 8 or 16 posted data (128B or 256B depending on max payload size)
7	0h	RO	Reserved
6:4	0x1	RW	Upstream Non-Posted Request Size (UNRS) Sets the size for splitting upstream memory read requests. Requests will be split on naturally aligned addresses. Defined encodings for this field are: 000b: 128 byte boundaries. 001b: 256 byte boundaries. 010b: 512 byte boundaries. 011b - 110b: Reserved. 128 byte boundaries. 111b: 64 byte boundaries. Note: This register is per-port. Software can program the request size to be different for different ports. Only '000b', '001b' and '111b' are supported. '010b' is not a valid setting. This field is only used if the Upstream Non-Posted Split Disable is '0'.
3	0h	RO	Reserved
2:0	0x1	RW	Upstream Posted Request Size (UPRS) Sets the size for splitting upstream memory write requests. Requests will be split on naturally aligned addresses. Defined encodings for this field are: 000b: 128 byte boundaries. 001b: 256 byte boundaries. 010b: 512 byte boundaries. 011b - 110b: Reserved. 128 byte boundaries. 111b: 64 byte boundaries. This field must not be set more than the effective Maximum Payload Size (function of both DCAP.MPS and DCTL.MPS). Note: This register is per-port. Software can program the request size to be different for different ports. Only '000b', '001b' and '111b' are supported. '010b' is not a valid setting. This field is only used if the Upstream Posted Split Disable is '0'. This register has no effect on posted messages which are never split.