ECC Error Log 0 (ECCERRLOG0_0_0_0_MCHBAR) – Offset E048 - 1.3 - ID:764981 | 13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

ID	Date	Version	Classification
764981	07/13/2023		Public

ECC Error Log 0 (ECCERRLOG0_0_0_0_MCHBAR) – Offset E048

This register logs ECC error information. Read only register/s, please refer to doc #655741 for details.

Bit Range	Default	Access	Field Name and Description
31:29	0x0	RO/V/P	Error Bank (ERRBANK) This field holds the Bank Address of the read transaction that had the ECC error.
28:27	0x0	RO/V/P	Error Rank (ERRRANK) This field holds the Rank ID of the read transaction that had the ECC error. If ddr_1dpc_split_ranks_on_sub-channel feature is enabled then rank 1 is actually logged as rank 3.
26:24	0x0	RO/V/P	Error Chunk (ERRCHUNK) Holds the chunk number of the error stored in the register.
23:16	0x0	RO/V/P	Error Syndrome (ERRSYND) This field contains the error syndrome. A value of 0xFF indicates that the error is due to poisoning.
15:4	0h	RO	Reserved
3	0x0	RW/1C/V/P	Multi-Bit Error Overflow (MERR_OVERFLOW) This bit is set when a correctable single-bit error occurs on a memory read data transfer. When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors, until this bit is cleared. A multiple bit error that occurs after this bit is set will override the address/error syndrome information. This bit is cleared when the corresponding bit in 0.0.0.PCI.ERRSTS is cleared.
2	0x0	RW/1C/V/P	Multi-Bit Error Status (MERRSTS) This bit is set when an uncorrectable multiple-bit error occurs on a memory read data transfer. When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared. This bit is cleared when the corresponding bit in 0.0.0.PCI.ERRSTS is cleared.
1	0x0	RW/1C/V/P	Correctable Single-Bit Error Overflow (CERR_OVERFLOW) This bit is set when a correctable single-bit error occurs on a memory read data transfer. When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors, until this bit is cleared. A multiple bit error that occurs after this bit is set will override the address/error syndrome information. This bit is cleared when the corresponding bit in 0.0.0.PCI.ERRSTS is cleared.
0	0x0	RW/1C/V/P	Single Bit Error Status (CERRSTS) This bit is set when a correctable single-bit error occurs on a memory read data transfer. When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors, until this bit is cleared. A multiple bit error that occurs after this bit is set will override the address/error syndrome information. This bit is cleared when the corresponding bit in 0.0.0.PCI.ERRSTS is cleared.