Frame Length Adjustment (FLADJ) – Offset 61 - 1.3 - ID:764981 | 13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 2)
- DMI VCm Resource Control (DMIVCMRCTL_0_0_0_DMIBAR)
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
- Egress Port Virtual Channel Control (EPPVCCTL_0_0_0_PXPEPBAR)
- Egress Port Element Declaration Capability (EPESD_0_0_0_PXPEPBAR)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D13:F0 USB Host Controller (xHCI) Registers
D13:F0 USB Host Controller MBAR Registers
D13:F1 USB Device Controller (xDCI) Configuration Registers
D13:F2-3 Thunderbolt DMA Device Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D5:F0 Image Processing Unit Registers
D6:F0 PCI Express* Controller Registers (part 1)
D6:F0 PCI Express* Controller Registers (part 2)
- Feature Control 2 (FCTL2)
D7:F0-3 Thunderbolt PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Frame Length Adjustment (FLADJ) – Offset 61

This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written into these six bits, the length of the frame is adjusted. Its initial programmed value is system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. This register should only be modified when the HChalted bit in the USBSTS register is a one. Changing value of this register while the host controller is operating yields undefined results.

Bit Range	Default	Access	Field Name and Description
7	0x0	RO	Reserved (RSVD) Read-Only. These bits are reserved for future use and should read as "00".
6	0x1	RO	No Frame Length Timing Capability (NO_FRAME_LENGTH_TIMING_CAP) This flag is set to 1 to indicate that the host controller does not support a programmable Frame Length Timing Value field.
5:0	0x20	RO	Frame Length Timing Value (FLTV) SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. Frame Length (number of High Speed bit times) FLADJ Value (decimal) (decimal) 59488 0 (00h) 59504 1 (01h) 59520 2 (02h) ... 59984 31 (1Fh) 60000 32 (20h) ... 60480 62 (3Eh) 60496 63 (3Fh) Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. Frame Length (# High Speed bit times) FLADJ Value

Bit Range

Default

Access

Field Name and Description

0x0

Reserved (RSVD)

Read-Only. These bits are reserved for future use and should read as "00".

0x1

No Frame Length Timing Capability (NO_FRAME_LENGTH_TIMING_CAP)

This flag is set to 1 to indicate that the host controller does not support a
programmable Frame Length Timing Value field.

5:0

0x20

Frame Length Timing Value (FLTV)

SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000.
Frame Length
(number of High Speed bit times) FLADJ Value
(decimal) (decimal)
59488 0 (00h)
59504 1 (01h)
59520 2 (02h)
...
59984 31 (1Fh)
60000 32 (20h)
...
60480 62 (3Eh)
60496 63 (3Fh)
Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. Frame Length (# High Speed bit times) FLADJ Value

Best Effort Service Latency. (BESL)

Serial Bus Release Number (SBRN) Best Effort Service Latency. (BESL)