Host Controller Misc Reg (HOST_CTRL_MISC_REG) – Offset 80B0 - 1.3 - ID:764981 | 13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

ID	Date	Version	Classification
764981	07/13/2023		Public

Host Controller Misc Reg (HOST_CTRL_MISC_REG) – Offset 80B0

Host Controller Misc Reg

Bit Range	Default	Access	Field Name and Description
31	0x0	RW	USB2 LTR Update Disable (USB2_LTRUPDT_DIS) This controls the inclusion of the USB2 LTR based on link state. Setting this bit will disable USB2 LTR and will expose a NO Requirement from USB2 thus not impacting the aggregated LTR vaule for the controller.
30	0x0	RW	USB2 Line State Debounce During Port Reset Policy (USB2_LINE_STATE_DEBOUNCE_DURING_PORT_RESET_POLICY) This register controls how the debounce is enforced during the Port Reset phase. 0 do not enable the line state debounce during port reset. 1 enable the line state debounce during port reset.
29	0x0	RW	TTE PEXE Credit Fix Disable (TTE_PEXE_CREDIT_FIX_DISABLE) When set, it disables a fix implemented to re-deem PEXE credits when a port is disconnected
28	0x0	RW	TTE Scheduling policy (TTE_SCHEDULING_POLICY) This register controls a fix made to prevent over-scheduling by not account for 188B in each uFrame. Setting this bit will disable the fix and allow for over-scheduling.
27	0x0	RW	USB3 ITP Delta Timer Source Select (USB3_ITP_DELTA_TIMER_SOURCE_SELECT) This register selects the source for the delta timer tracking used for ITP generation. 0 the source is a 16.666 ns tick generated from a crystal reference clock 1 - the source is a 16.666 ns tick generated from the aux_cclk. This field needs to remain in sync with Frame Timer Source Select to ensure the are both set or both cleared. There is no support for any other combination.
26	0x0	RW	Frame Timer Source Select (FRAME_TIMER_SOURCE_SELECT) This register controls the source for the frame timer. 0 the source for the frame timer is a crystal reference clock 1 the source for the frame timer is the aux_cclk.
25	0x0	RW	uFrame Masking Enable (UFRAME_MASKING_ENABLE) If set, enables the uFrame tick to be masked due to ports being in U3/NC. This controls a fix made to disable the auto masking of uFrame tick due to port state without any pipeline idle condition. When cleared, the controller relies on gating of frame timer due to proper port state and idleness tracking from the pipeline.
24	0x0	RW	Late FID Check Disable (LATE_FID_CHECK_DISABLE) This register disables the Late FID Check performed when starting an ISOCH stream.
23	0x1	RW	Late FID TTE count adjust Disable (DIS_LATE_FID_TTE_CNT_ADJ) 0: the value of frame late skip count starts at 1 for TTE eps and 0 for non tte eps. this represents an adjustment for the number of SI missed. 1: the value of frame late skip count starts at 0 for both TTE eps and non TTE eps.
22	0x0	RW	Late FID difference calculation legacy (DIS_DIF_CAL_LEGACY) 0: late uframeid uses the new difference calculation to compute how may SI the TD is late. 1: late uframeid uses the legacy difference calculation to compute how may SI the TD is late.
21	0x0	RW	ERDY flag Disable (ERDY_FLAG_DIS) 0: An ERDY received on any interrupt EP will force the backbone clock high untill the next uframe to allow that eps trm pending mask to be cleared 1: This feature is disabled
20	0x0	RW	Enable LTR DB Device Clear (EN_LTR_DB_DEV_CLR) 1: TDB 0: Enable bit operation
19	0x0	RW	USB2 Resume Cx Inhibit Disable (USB2_RESUME_CX_INHIBIT_DISABLE) Controls if USB2 L1 Resume is allowed to contribute to DMA Active which will inhibit Cx state. 0 USB2 L1 Resume is allowed to inhibit Cx via DMA Active 1 USB2 L1 Resume is NOT allowed to inhibit Cx via DMA Active When cleared, Cx will only be inhibited when the DMA traffic for the port begins.
18	0x0	RW	Late FID TTE Disable (LATE_FID_TTE_DIS) 0: Late Frame ID Check is enabled for TTE Endpoints 1: Late Frame ID Check is disabled for TTE Endpoints
17	0x0	RW	Late FID uframe Check Disable (LATE_FID_UFRAME_CHK_DIS) 0 Frame ID Match only asserts in uframe 7 for non-TTE Endpoints Frame before match 1 Frame ID Match can assert in any uframe
16	0x0	RW	Late FID Extra Interval (LATE_FID_EXTRA_INTER) This register controls the extra number of intervals added onto the advancing of late FID check escentially a bias used to correct for possible errors in implementation
15:0	0x37F	RW	Valid Isoch Scheduling Range (VALID_ISOCH_SCHEDULING_RANGE) This register defines the window in miliseconds from the current Frame that will be considered for scheduling in an upcoming Frame. Anything scheduled outside of this window will be considered as late and will trigger the Missed Service Error.