L1 Sub-States Control 1 (L1SCTL1) – Offset 208 - 1.3 - ID:764981 | 13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

ID	Date	Version	Classification
764981	07/13/2023		Public

L1 Sub-States Control 1 (L1SCTL1) – Offset 208

L1 Sub-States Control 1

Bit Range	Default	Access	Field Name and Description
31:29	0x0	RW	L1.2 LTR Threshold Latency Scale Value (L12LTRTLSV) This field contains the L1.OFF LTR Threshold Latency Scale Value for this particular Root Port. The value in this field, together with L12LTRTLV is compared against both the snoop and non-snoop LTR values of the device. 000b: L12LTRSTLV times 1 ns 001b: L12LTRSTLV times 32 ns 010b: L12LTRSTLV times 1024 ns 011b: L12LTRSTLV times 32768 ns 100b: L12LTRSTLV times 1048576 ns 101b: L12LTRSTLV times 33554432 ns Others values are reserved. This field must be programmed prior to enabling L1.OFF.
28:26	0h	RO	Reserved
25:16	0x0	RW	L1.2 LTR Threshold Latency Value (L12LTRTLV) This field contains the L1.2 LTR Threshold Latency Value for this particular Root Port. The value in this field, together with L12LTRTLSV is compared against both the snoop and non-snoop LTR values of the device. This field must be programmed prior to enabling L1.OFF.
15:8	0x0	RW	Common Mode Restore Time (CMRT) This is the Tcommon_mode time (in us) the Root Port needs to continue sending TS1 and refrain from sending TS2 in Recovery state to allow the TX common mode to be established prior to sending TS2. The timer starts from the time when the first TS1 has been sent and the receiver has detected un-squelch. The value in this field defines the time in micro-seconds. This field must be programmed prior to enabling L1.OFF.
7:6	0h	RO	Reserved
5	0x0	RW	L1 Substate Exit Control (L1SSEC) L1.Substate the Port must initiate the CLKREQ# Acceleration Link Activation process. Apart from that, once the Link reaches L0, the Port must continue to attempt to maintain the Link in L0 for as long as this bit remains Set. However, if the Upstream Port request for L1 entry, the Downstream Port will proceed to allow L1 entry but will not re-enter L1.1 or L1.2.
4	0x0	RW	CLKREQ# Acceleration Interrupt Enable (L1SSEIE) When set this bit enables the generation of an interrupt to indicate the completion of the CLKREQ# Accelration Link Activation process
3	0x0	RW	ASPM L1.1 Enable (AL11E) When set, this bit indicates that ASPM L1.SNOOZ substates are enabled. Required for both upstream and downstream ports. Note: If STRPFUSECFG.mPHYIOPMDIS is '1', hardware will always see '0' as an output from this register. BIOS reading this register should always return the correct value.
2	0x0	RW	ASPM L1.2 Enable (AL12E) When set, this bit indicates that ASPM L1.OFF substates are enabled. Required for both upstream and downstream ports. Note: If STRPFUSECFG.mPHYIOPMDIS is '1', hardware will always see '0' as an output from this register. BIOS reading this register should always return the correct value.
1	0x0	RW	PCI-PM L1.1 Enable (PPL11E) When set, this bit indicates that PCI-PM L1.SNOOZ power management feature is enabled. If L1.OFF is enabled, L1.SNOOZ must also be enabled. This field must be programmed prior to enabling ASPM L1. Note: If STRPFUSECFG.mPHYIOPMDIS is '1', hardware will always see '0' as an output from this register. BIOS reading this register should always return the correct value.
0	0x0	RW	PCI-PM L1.2 Enabled (PPL12E) When set, this bit indicates that PCI-PM L1.OFF power management feature is enabled. L1.OFF can only be enabled if the platform supports bi-directional CLKREQPLUS#. This field must be programmed prior to enabling ASPM L1. Ports that support L1.OFF shall support Latency Tolerance Reporting. Note: If STRPFUSECFG.mPHYIOPMDIS is '1', hardware will always see '0' as an output from this register. BIOS reading this register should always return the correct value.