PCI Command (PCICMD_0_0_0_PCI) – Offset 4 - 1.3 - ID:764981 | 13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

ID	Date	Version	Classification
764981	07/13/2023		Public

PCI Command (PCICMD_0_0_0_PCI) – Offset 4

Since Device #0 does not physically reside on PCI_A many of the bits are not implemented.

Bit Range	Default	Access	Field Name and Description
15:10	0h	RO	Reserved
9	0x0	RO	Fast Back To Back Enable (FB2B) Fast Back-to-Back Enable: This bit controls whether or not the master can do fast back-to-back write. Since device 0 is strictly a target this bit is not implemented and is hardwired to 0. Writes to this bit position have no effect.
8	0x0	RW	SERR Reporting Enable (SERRE) SERR Enable: This bit is a global enable bit for Device 0 SERR messaging. The CPU communicates the SERR condition by sending an SERR message over DMI to the PCH. 1: The CPU is enabled to generate SERR messages over DMI for specific Device 0 error conditions that are individually enabled in the ERRCMD and DMIUEMSK registers. The error status is reported in the ERRSTS, PCISTS, and DMIUEST registers. 0: The SERR message is not generated by the Host for Device 0. This bit only controls SERR messaging for Device 0. Other integrated devices have their own SERRE bits to control error reporting for error conditions occurring in each device. The control bits are used in a logical OR manner to enable the SERR DMI message mechanism. OPI N/A
7	0x0	RO	Address/Data Stepping (ADSTEP) Address/Data Stepping Enable: Address/data stepping is not implemented in the CPU, and this bit is hardwired to 0. Writes to this bit position have no effect.
6	0x0	RW	Parity Error Response Enable (PERRE) OPI - N/A Parity Error Enable: Controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set. 0: Master Data Parity Error bit in PCI Status register can NOT be set. 1: Master Data Parity Error bit in PCI Status register CAN be set.
5	0x0	RO	Video Palette Snooping (VGASNOOP) VGA Palette Snoop Enable: The CPU does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect.
4	0x0	RO	Memory Write and Invalidate Enable (MWIE) Memory Write and Invalidate Enable: The CPU will never issue memory write and invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect.
3	0x0	RO	Special Cycle Enable (SCE) Reserved per PCI-Express and PCI bridge spec.
2	0x1	RO	Bus Master Enable (BME) Bus Master Enable: The CPU is always enabled as a master on the backbone. This bit is hardwired to a 1. Writes to this bit position have no effect.
1	0x1	RO	Memory Access Enable (MAE) Memory Access Enable: The CPU always allows access to main memory, except when such access would violate security principles. Such exceptions are outside the scope of PCI control. This bit is not implemented and is hardwired to 1. Writes to this bit position have no effect.
0	0x0	RO	I/O Access Enable (IOAE) I/O Access Enable: This bit is not implemented in the CPU and is hardwired to a 0. Writes to this bit position have no effect.