Power Management Control (PMCTRL_REG) – Offset 80A4 - 1.3 - ID:764981 | 13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

ID	Date	Version	Classification
764981	07/13/2023		Public

Power Management Control (PMCTRL_REG) – Offset 80A4

Power Management Control

Bit Range	Default	Access	Field Name and Description
31	0x0	RW	Async PME Source Enable (ASYNC_PME_SRC_EN) This field allows the async PME source to be allowed to generate PME. This is specifically required for SOCs that do not allow for any clock other than RTC to be available during RTD3.
30	0x1	RW	Legacy PME Source Enable (LEGACY_PME_SRC_EN) This field allows the legacy PME source to be used in PME generation. The legacy source in in reference to the source prior to the RTD3 changes.
29	0x0	RW	Reset Warn Power Gate Trigger Disable (RESET_WARN_PWR_GATE_TRIGGER_DISABLE) This field controls the actions taken for due to reset warn. 0 - Reset Warn will trigger a HW autonomous Power Gate 1 - Reset Warn will not trigger a HW autonomous Power Gate
28	0x0	RW	Clear PME Flag (CLR_PME_FLAG_PULSE_AUX_CCLK) Internal PME flag Clear This Write-Only bit can be used to clear the internal PME flag. SW write to 1 will clear the PME flag. SW write to 0 will have no effect and be ignored by the controller. Read always return 0
27	0x1	RW	Disable RTD3 power gating when in D3 (DIS_D3_PG) Disable RTD3 power gating when in D3 and context save operation is not performed
26	0x0	RW	XLFPS Count Source (XLFPSCOUNTSRC) XLFPSCOUNTSRC (Source for LFPS OFF Counter) 0: Central RTC Counter for LFPS detection 1: Local Counter for LFPS detection
25	0x0	RW	X Enable LFPS Filtering on RTC (XELFPSRTC) XELFPSRTC (Enable LFPS Filtering on RTC) 0: Use Oscillator clock for LFPS Filtering during P3 1: Use RTC Clock for LFPS Filtering during P3
24	0x1	RW	X ModPhy Sustain Well Power Gate Disable for D0I2 (XMPHYSPGDD0I2) XMPHYSPGDD0I2 (ModPhy Sus Well Power Gate Disable for D0I2) 0: Modphy sustain well power gating enabled 1: Modphy sustain well power gating disabled
23	0x0	RW	X ModPhy Sustain Well Power Gate Disable for D0I3 (XMPHYSPGDD0I3) XMPHYSPGDD0I3 (ModPhy Sus Well Power Gate Disable for D0I3) 0: Modphy sustain well power gating enabled 1: Modphy sustain well power gating disabled
22	0x0	RW	X ModPhy Sustain Well Power Gate Disable for RTD3 (XMPHYSPGDRTD3) XMPHYSPGDRTD3 (ModPhy Sustain Well Power Gate Disable for RTD3) 0: Modphy sustain well power gating enabled. 1: Modphy sustain well power gating disabled.
21:18	0xB	RW	D3 RTC Port Timer Tick Multiplier (XD3RTCPTTM) XD3RTCPTTM (D3 RTC Port Timer Tick Multiplier) This register will be the multiplication factor for determining USB3 Wake Detection Frequency and RXDET based on the XD3RTCPTTC value. If XD3RTCPTTC is 9h and this register is Bh, frequency for RXDET H8EXIT detection while MODPHY SUS Power gating is enabled would be 99ms.
17	0x0	RW	U3 LFPS Periodic Sampling ON Time Control (U3_LFPS_PRDC_SAMPLING_ON_TIME_CTRL) This field controls the ON time for the LFPS periodic sampling for USB3 ports. 0 ON time is 2 rtc clocks 1 ON time is 3 rtc clocks Note: This field is ignored if USB3 PHY SUS Well Power Gating is enabled.
16	0x1	RW	AON LFPS Detector Enable Mode (AON_LFPS_DETECTOR_EN_MODE) 1 - Allow the LFSP Detector in AON to own LFPS detection when the port is in PS3 for U2/U3 - not RxD regardless of port ownership. 0 - Allow the LFPS Detector in AON to own the LFPS detection only when the AON owns the port and in U2/U3 - not RxD
15:8	0x50	RW	SS U3 LFPS Detection Threshold (SS_U3_LFPS_DETECTION_THRESHOLD) This field controls the threshold used to determine when a valid U3 Wake is detected through when using the unfiltered LFPS source. The value on this field will reflect the binary count required to have been detected on the counter being clocked by the unfiltered lfps source to result in a valid U3 wake detection.
7:4	0x9	RW	U3 LFPS Periodic Sampling Off Time Control (SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL) This field controls the OFF time for the LFPS periodic sampling for USB3 Ports 0x0 periodic sampling is disabled. 0x1 OFF time is 1ms 0x2 OFF time is 2ms 0xF OFF time is 15ms The ON Time is determined by the amount of time required to reliably determine if there is a valid LFPS and is HW implementation specific. A speed up mode shall be implemented where this field is in units of us. i.e. 0x1 = 1 us OFF time, 0x2 = 2 us OFF time, etc.
3	0x0	RW	PS3 LFPS Source Select (PS3_LFPS_SRC_SEL) 0 LFPS Source is unfiltered 1 LFPS Source is filtered (Rx-Elec-Idle) LFPS Source is Rx-Elec-Idle for any non PS3 state.
2	0x1	RW	XHCI Engine Autonomous Power Gate Exit Reset Policy (XHC_AUTO_PWRGATE_EXITRST_POLICY) Controls when the xHCI engine is brought out of reset due to a power ungate. 0 Engine is brought out of reset when D3 to D0 is triggered. This allows for a quick power up sequence while leaving the virtual PCIe LTSSM in L23 is power ungate is not due to D3 to D0. 1 Engine is brought out of reset along with the rest of the IP. This is required for PMC save/restore flow.
1	0x0	RW	USB2 Port Wake Unit Coupling Policy (USB2_PORT_WAKE_COUPLING_POLICY) Controls the trigger for USB2 Port Wake Units to initiate Port Level Power Off Preparation. 0 RTD3 triggered 1 - Port Triggered when in L1, L2 or Disabled, Disconnected
0	0x0	RW	USB3 Port Wake Unit Coupling Policy (USB3_PORT_WAKE_COUPLING_POLICY) Controls the trigger for USB3 Port Wake Units to initiate Port Level Power Off Preparation. 0 - RTD3 Triggered 1 - Port Triggered when in PS3 due to RxDetect, U3, U2 or Disabled