13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
764981 | 07/13/2023 | Public |
Top of Low Usable DRAM (TOLUD_0_0_0_PCI) – Offset BC
This 32 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics memory and Graphics Stolen Memory are within the DRAM space defined. From the top, the Host optionally claims 1 to 64MBs of DRAM for internal graphics if enabled, 1or 2MB of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for TSEG if enabled.
Programming Example:
C1DRB3 is set to 4GB
TSEG is enabled and TSEG size is set to 1MB
Internal Graphics is enabled, and Graphics Mode Select is set to 32MB
GTT Graphics Stolen Memory Size set to 2MB
BIOS knows the OS requires 1G of PCI space.
BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable by the system. This 20MB range at the very top of addressable memory space is lost to APIC and Intel TXT.
According to the above equation, TOLUD is originally calculated to: 4GB = 1_0000_0000h
The system memory requirements are: 4GB (max addressable space) - 1GB PCI space) - 35MB (lost memory) = 3GB - 35MB (minimum granularity) = 0_ECB0_0000h
Since 0_ECB0_0000h (PCI and other system requirements) is less than 1_0000_0000h, TOLUD should be programmed to ECBh.
These bits are Intel TXT lockable.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:20 | 0x1 | RW/L | (TOLUD) This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system. Address bits 31 down to 20 programmed to 01h implies a minimum memory size of 1MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register. |
19:1 | 0h | RO | Reserved |
0 | 0x0 | RW/L | (LOCK) This bit will lock all writable settings in this register, including itself. |