USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1) – Offset 80F0 - 1.3 - ID:764981 | 13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

ID	Date	Version	Classification
764981	07/13/2023		Public

USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1) – Offset 80F0

These set of registers is used to control jey USB set of timers. They are spread over 4 registers each 32 bits wide.

Bit Range	Default	Access	Field Name and Description
31:24	0x31	RW	FS/LS Mode SE0 Disconnect Delay (FSLS_SE0_DIS_DEL_7_0) Number of microseconds of SE0 in FS/LS mode to register disconnect had occurred.
23	0x0	RW	Enable SNPS PHY Fix (EN_SNPS_PHY_FIX) Enable SNPS PHY Fix: 1: When set, termselect will assert at the start of EOR. Fslsserialmode will also deassert at the same clock as txenb. 0: Legacy behavior for Intel PHY.
22	0x1	RW	Enable L1 Disconnect in L0 (EN_L1_DISC_IN_L0) Enable Pseudo L0 state when transition from L1 to L2 due to disconnect: 1: When set, {L1 suspendm, L2 suspendm} will go from 01->11->10 to allow the USB2 PHY to exit L1 and enter L2 for deeper PM 0: Legacy behavior (01->10)
21	0x0	RW	Disable Purge On Setup (DIS_PURGE_ON_SETUP_FIX) To disable the fix for SETUP purge that match for both device address and endpoint number: 0: Only allow purge for SETUP when both device address and endpoint number are matched. 1: Revert back to old behaviour that purge is allowed when either device address or endpoint number is matched.
20	0x0	RW	L1 Exit Recovery Mode (L1_EXIT_RECOVERY_MODE) Mode for extended L1 Exit recovery delay: 0: 12us 1: 50us
19	0x1	RW	L1 Timeout Increment Mode (L1_TO_INCR_MODE) Mode select for L1 Timeout increments: 0: time out increments are in 125us 1: L1 Timeout increments are in 256us. Refer to USB2 PORTHLPMC.L1 Timeout in XHCI Spec for additional details
18	0x0	RW	Reserved (RSVD1) Reserved
17	0x0	RW	Enable Detect Minimal Packet EOP (EN_DETECT_NOMINAL_PKT_EOP) 0: Detect minimal packet EOP. 1: Detect nominal packet EOP.
16	0x0	RW	Disable Chirp Response (DIS_CHIRP_RESPONSE) 0: Normal 1: Force full speed on host ports (disable chirp response)
15	0x0	RW	Disable 192 Byte Limit Check (DIS_192B_LIM) 0: Enforce 192 byte limit on complete-split INs. Treat any packet ) 192 as babble case. 1: Disable 192 byte limit check.
14	0x0	RW	External Provided FS/LS Disconnect (EXT_FSLS_DIS) 0: Internal FS/LS Disconnect from linestate(1:0) 1: External provided FS/LS Disconnect from hostdisconnect input
13:12	0x0	RW	UTMI Reset Source Select (UTMI_RST_SEL) Select UTMI Reset Source (FRD UTMI Reset Only) 00: HCReset or Force PHY Reset or internal reset after disconnect/suspend for restart (default) 01,11: UTMI reset = ~UTMI suspendm 10: UTMI reset = ~UTMI suspendm and synchronization to port clk.
11	0x0	RW	Disable HS Disconnect Window (DIS_HS_DIS_WIN) 0: Enable HS Disconnect Window Function 1: Disable HS Disconnect Window Function
10	0x0	RW	Disable Port Error Detection (DIS_PERR_DET) 0: Enable Port Error Detection (default) 1: Disable Port Error Detection
9	0x1	RW	Disable Peek Function for ISO-OUT (DIS_PF_IOUT) 0: Enable Peek function for ISO-OUT (default) 1: Disable Peek function for ISO-OUT
8	0x1	RW	Drive Resume-K FS/LS Serial Interface (DRV_RESK_FSLS_SER) 0: Drive Resume-K on parallel Interface 1: Drive Resume-K directly on FS/LS Serial Interface (default)
7	0x1	RW	Enable USB2 Drop-Ping (EN_U2_DROP_PING) 0: Disable Drop-Ping Function in USB2 Protocol (default) 1: Enable Drop-Ping Function in USB2 Protocol
6	0x0	RW	Enable USB2 Force-Ping (EN_U2_FORCE_PING) 0: Disable Force-Ping Function in USB2 Protocol (default) 1: Enable Force-Ping Function in USB2 Protocol
5	0x1	RW	Enable USB2 Auto-Ping (EN_U2_AUTO_PING) 0: Disable Auto-Ping Function 1: Enable Auto-Ping Function in USB2 Protocol (default)
4	0x0	RW	Disable PHY SuspendM (DIS_PHY_SUSM) 0: PHY is suspend=U3,U2,disconnect (default) 1: Disable PHY SuspendM in All States
3	0x0	RW	UTMI Internal Clock Gate Disable (UTMI_INT_CG_DIS) 0: Normal operation (internal clock gated in U2,U3,disconnect) 1: UTMI Internal Clock Gate Disable
2	0x0	RW	Disable PHY SuspendM in Disconnect State (DIS_PSUSM_DS) 0: PHY is suspendM=0 in Disconnect State (default) 1: Disable PHY SuspendM in Disconnect State
1	0x0	RW	Force PHY Reset (FORCE_PHY_RST) 0: Normal Operation (default) 1: Force PHY Reset
0	0x0	RW	USB2 Accelerated Simulation Timing (U2_ACC_SIM_TIM) 0: Normal Operation (default - FPGA/ASIC) 1: USB2 Accelerated Simulation Timing (default - simulation)