USB2 Power Management Control (USB2PMCTRL_REG) – Offset 81C4 - 1.3 - ID:764981 | 13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

13th Generation Intel® Core™ Processor Datasheet, Volume 2 of 2

ID	Date	Version	Classification
764981	07/13/2023		Public

USB2 Power Management Control (USB2PMCTRL_REG) – Offset 81C4

USB2 Power Management Control

Bit Range	Default	Access	Field Name and Description
31	0x0	RW	RF Power Gate Fix Disable (DIS_RFPGFIX) 0: Enable RF Power gating fix (Default) 1: Disable RF Power gating fix
30:25	0x0	RW	Reserved (RSVD3) Reserved
24	0x0	RW	SNPS PHY OPMODE Normal Enable (SNPSPHYOPNORMEN) 1: Enables OPMODE == Normal during suspendm/sleepm assertion 0: OPMODE == Disable Bit Stuff/NRZI during suspendm/sleepm assertion
23	0x1	RW	SNPS PHY Resume Bypass Path Disable (SNPSPHYRESBYPDIS) 1: Disables the resume signaling through the bypass path 0: Enables the resume signaling through the bypass path
22:21	0x0	RW	L1 Timeout Override (L1TOUTOVR) Overrides and ignores SW programmed values for L1 Timeout on all ports to 11: 60 us 10: 40 us 01: 20 us 00: Accepts L1 Timeout value from SW (no override)
20	0x0	RW	L1 BESL/BESLD Override (L1BESLOVR) 1: Overrides BESL/BESLD to zero on all ports and ignores SW programmed values 0: Accept BESL/BESLD values from SW (no override)
19	0x0	RW	Disable RTC Sus Power Gating Control (DISRTCSPGC) 1: Disables the RTC Sus PG SM from asserting sus_pwr_req to PMC, legacy path is used instead 0: Enables the RTC Sus PG SM to assert sus_pwr_req to PMC
18:16	0x2	RW	L1 USB2 PLL Spin Up Time (L1USB2PLLSUT) PLL Spin Up Time in 10us increments (0-70us).
15	0x0	RW	Reserved (RSVD2) Reserved
14	0x0	RW	RTC Resume Disable (DIS_RTCRSM) 1: When set, RTC resume will be disable and fallback to use portmgr for resumes 0: When cleared, RTC resume will take over port manager's U3 resume
13	0x1	RW	Bypass Suspend SM (BYPSUSSM) 1: When set, Suspend SM is bypassed and L1/L2 suspendm from the controller goes directly to the PHY 0: When cleared, Suspend SM controls the L1/L2 suspendm to the PHY
12	0x0	RW	USB2 HOST PHY UTMI Clock Gate Disable Policy (U2HPUCGDP) This controls the policy for Host PHY UTMI Clock Gating. When Set HOST PHY UTMI Clock Gating is disabled else Host PHY UTMI Clock Gating is enable
11	0x1	RW	USB2 PHY SUS Power Gate PORTSC Block Policy (U2PSPGPSCBP) This controls the policy for blocking PORTSC Updates while the USB2 PHY SUS Well is power gated. When set, the controller will block any updates to the PORTSC caused by port status change if the USB2 PHY SUS is power gated. 0 Do not
10:8	0x1	RW	USB2 PHY SUS Well Power Gate Entry Hysteresis Count (U2PSPGEHC) This controls the amount of hysteresis time the controller will enforce after detecting the USB2 PHY SUS Power Gate entry condition. 0h 0 clocks 1h 32 clocks 2h 64 clocks 3h 128 clocks 4h 256 clocks 5h 512 clocks 6h 1024 clocks 7h 2048 clocks
7:4	0x0	RW	USB2 PHY SUS Power Gate PORTSC Block Policy (U2CLPGLAT) This field represents the worst case latency for the USB2 Common Lane to enter and exit its power gate state. This fields is required to be compared to a ports HIRD/HIRD value for the ports that have allowed L1 to L2 mapping to determine if the Common Lane can be allowed to power off. If the power gate entry/exit latency is greater than the HIRD/HIRDD then the common lane should not be allowed to power gate as this will result in a L1 exit violation. 0h 100 us 1h 200 us 2h 300 us Eh 1500us Fh 1600 us
3:2	0x2	RW	USB2 PHY SUS Well Power Gate Policy (U2PSUSPGP) This field controls when to enable the USB2 PHY SUS Well Power Gating when the proper conditions are met. 00 USB2 PHY SUS Power Gating is Disabled. 01 USB2 PHY SUS Power Gating is Enabled in Only D0 and D0i2 (Excludes D0i3 and D3) 10 USB2 PHY SUS Power Gating is Eanabled in only in D0, D0i2 and D0i3 (Excludes D3) 11 USB2 PHY SUS Power Gating is Eanabled in D0/D0i2/D0i3/D3
1:0	0x0	RW	Reserved (RSVD1) Reserved