BIST, Header Type, Latency Timer, And Cache Line Size (IDE_HOST_BIST_HTYPE_LT_CLS) – Offset c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

BIST, Header Type, Latency Timer, And Cache Line Size (IDE_HOST_BIST_HTYPE_LT_CLS) – Offset c

This register contains the BIST, header type, latency timer, and cache line size values.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Built In Self Test (BIST) Not implemented. Hardwired to 0.
23	1h	RO/V	Header Type 1 (HTYPE1) This bit identifies whether or not the device contains multiple functions. If the bit is 0, then the device is single function. If the bit is 1, then the device has multiple functions.
22:16	0h	RO	Header Type 0 (HTYPE0) This field identifies the layout of the second part of the predefined header (beginning at byte 10h in Configuration Space). The encoding 00h specifies the non-bridge Configuration Space Header. The encoding 01h specifies the PCI-to-PCI bridge Configuration Space Header. The encoding 02h specifies the CardBus bridge Configuration Space Header. All other encodings are reserved. Hardwired to 0 to identify the non-bridge Configuration Space Header.
15:8	0h	RO	Latency Timer (LT) Not implemented. Hardwired to 0.
7:0	0h	RO	Cache Line Size (CLS) Not implemented. Hardwired to 0.

IDE Primary Command Block IO BAR (IDE_HOST_PCMDIOBAR)

Class Code And Revision ID (IDE_HOST_CC_RID) IDE Primary Command Block IO BAR (IDE_HOST_PCMDIOBAR)