CPU Early Power-on Configuration (CPU_EPOC) – Offset 18ec - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
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GPIO Commumity 5
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- AHCI Index Register (INDEX)
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
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SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
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SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

CPU Early Power-on Configuration (CPU_EPOC) – Offset 18ec

Bit Range	Default	Access	Field Name and Description
31:22	0h	RO	Reserved
21:20	0h	RO/V	Crystal Frequency[2:1] (XTAL_FREQ_MSB) Along with XTAL_FREQ_LSB the 3 bit field reflects the frequency of the crystal (aka NSSC) clock used by the CPU and PCH Encoding: 000b -24MHz 001b -19.Mhz 010b -38.4 Mhz Others - Reserved
19	0h	RO/V	EPOC Data[19] (EPOC_DATA_19) DAM ( Delayed Authentication Mode
18	0h	RO/V	EPOC Data[18] (EPOC_DATA_18) Debug Consent
17	0h	RO/V	Crystal Frequency [0] (XTAL_FREQ_LSB) See XTAL_FREQ_MSB
16	0h	RO	Reserved
15	0h	RO/V	EPOC Data[15] (EPOC_DATA_15) the values comes from DRV_CPU_EPOC from PMU space which is driven by PMC FW.
14:8	0h	RO/V	EPOC Data[14:8] (EPOC_DATA_14_8) These bits come from PMC soft straps reserved for straps that must be available to the CPU prior to PLTRST# de-assertion. Note: Any straps that only need to be available after OPI is up should be sent as part of the strap set message from SPI instead of being reserved in the PMC straps, defined in EPOC, and sent by the PMC.
7:3	0h	RW/L	EPOC Data [7:3] (EPOC_DATA_7_3) EPOC Data [7:3]
2	0h	RO	Reserved
1:0	0h	RW/L	EPOC Data [1:0] (EPOC_DATA_1_0) EPOC Data [1:0]

ADR Enable (ADR_EN)

Power Management Configuration Reg 4 (PM_CFG4) ADR Enable (ADR_EN)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

CPU Early Power-on Configuration (CPU_EPOC) – Offset 18ec