RIRB Write Pointer (RIRBWP) – Offset 58 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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RIRB Write Pointer (RIRBWP) – Offset 58

Bit Range	Default	Access	Field Name and Description
15	0b	WO	RIRB Write Pointer Reset (RIRBWPRST) Software writes a 1 to this bit to reset the RIRB Write Pointer to 0's. The RIRB DMA engine must be stopped prior to resetting the Write Pointer or else DMA transfer may be corrupted. This bit will always be read as 0.
14:8	-	-	Reserved
7:0	00h	RO/V	RIRB Write Pointer (RIRBWP) Indicates the last valid RIRB entry written by the DMA controller. Software reads this field to determine how many responses it can read from the RIRB. The value read indicates the RIRB Write Pointer offset in 2 Dword RIRB entry units (since each RIRB entry is 2 Dwords long). Supports up to 256 RIRB entries (256 x 8B=2KB). This field may be read while the DMA engine is running.

Bit Range

Default

Access

Field Name and Description

RIRB Write Pointer Reset (RIRBWPRST)

Software writes a 1 to this bit to reset the RIRB Write Pointer to 0's. The RIRB DMA

engine must be stopped prior to resetting the Write Pointer or else DMA transfer may

be corrupted. This bit will always be read as 0.

14:8

Reserved

7:0

00h

RO/V

RIRB Write Pointer (RIRBWP)

Indicates the last valid RIRB entry written by the DMA controller. Software reads this

field to determine how many responses it can read from the RIRB. The value read indicates

the RIRB Write Pointer offset in 2 Dword RIRB entry units (since each RIRB entry is 2

Dwords long). Supports up to 256 RIRB entries (256 x 8B=2KB). This field may be read while

the DMA engine is running.

Response Interrupt Count (RINTCNT)

RIRB Upper Base Address (RIRBUBASE) Response Interrupt Count (RINTCNT)