Immediate Command Status (ICS) – Offset 68 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Immediate Command Status (ICS) – Offset 68

Bit Range	Default	Access	Field Name and Description
14:2	-	-	Reserved
1	0b	RW/1C/V	Immediate Result Valid (IRV) This bit is set to a 1 by hardware when a new response is latched into the IR register. This is a status flag indicating that software may read the response from the Immediate Response register. Software must clear this bit (by writing a one to it) before issuing a new command so that the software may determine when a new response has arrived.
0	0b	RW/V	Immediate Command Busy (ICB) When this bit as read as a 0 it indicates that a new command may be issued using the Immediate Command mechanism. When this bit transitions from a 0 to a 1 (via software writing a 1), the controller issues the command currently stored in the Immediate Command register to the codec over the link. When the corresponding response is latched into the Immediate Response register, the controller hardware sets the IRV flag and clears the ICB bit back to 0. SW may write this bit to a 0 if the bit fails to return to 0 after a reasonable timeout period. Note that an Immediate Command must not be issued while the CORB/RIRB mechanism is operating, otherwise the responses conflict. This must be enforced by software.

Bit Range

Default

Access

Field Name and Description

14:2

Reserved

RW/1C/V

Immediate Result Valid (IRV)

This bit is set to a 1 by hardware when a new response is latched into the IR register.

This is a status flag indicating that software may read the response from the Immediate

Response register.

Software must clear this bit (by writing a one to it) before issuing a new command so that

the software may determine when a new response has arrived.

RW/V

Immediate Command Busy (ICB)

When this bit as read as a 0 it indicates that a new command may be issued using the

Immediate Command mechanism. When this bit transitions from a 0 to a 1 (via software

writing a 1), the controller issues the command currently stored in the Immediate

Command register to the codec over the link. When the corresponding response is

latched into the Immediate Response register, the controller hardware sets the IRV

flag and clears the ICB bit back to 0. SW may write this bit to a 0 if the bit fails

to return to 0 after a reasonable timeout period.

Note that an Immediate Command must not be issued while the CORB/RIRB mechanism is

operating, otherwise the responses conflict. This must be enforced by software.

DMA Position Lower Base Address (DPLBASE)

Immediate Response (IR) DMA Position Lower Base Address (DPLBASE)