Mode register (MODE) — Offset 318h
Configuration register for the main m2m modes.
Important configuration restrictions:
- Isoch is not supported by the m2m if DDRT is present on a channel.
- Isoch is not supported if any channel gets serviced by FNV.
- Mirroring and Isoch mode are mutually exclusive.
Whenever mirroring is enabled on a mesh2mem, then also following bits need to get set on that mesh2mem:
- Defeatures0[IngBypDis]=1 (functional requirement )
- Sysfeatures0[PrefDisable]=1 (functional requirement )
| Type | Size | Offset | Default |
|---|
| PCI | 32 bit | [B:30, D:12, F:0] + 318h | 00000000h |
Register Level Access:
| BIOS Access | SMM Access | OS Access |
|---|
| RW | R | R |
| Bit Range | Default & Access | Field Name (ID): Description |
|---|
| 31:14 | 0h RO | Reserved |
| 13 | 0h RW | NMCMODE: Near Memory Controller mode: When set, this indicates that the M2M is in an HBM configuration where the HBMtile is configured to handle route through or xtile 2lm NM transactions This should only be set on the M2M in the HBM tile. Do not set this if not in 2LM mode or not an HBM product where cross-tile 2LM or route through flows are applicable. 0: This M2M is not a HBM controller in cross-tile 2LM or route through 1: This M2M is a HBM controller in cross-tile 2LM or route through. |
| 12 | 0h RW | FMCMODE: Far Memory Controller mode: When set, this indicates that the M2M is in an HBM configuration where 2LM is enabled and this Memory controller handles the Far Memory(DDR). This should only be set on the M2M in the DDR tile, and not on the M2M in the HBM tile. Do not set this if not in 2LM mode or not an HBM product where cross-tile 2LM flows are applicable. 0: This M2M is not a Far Memory controller in cross-tile 2LM. 1: This M2M is a Far Memory controller in cross-tile 2LM. |
| 11 | 0h RW/P | ADDDC: Unused: available for ECO if necessary. |
| 10 | 0h RW/P | Reserved |
| 9 | 0h RW/P | MIRRORDDR4: DDR4 Mirroring (MirrorDDR4): Enable DDR4 mirroring. It is illegal to set this bit when Near Memory Caching is enabled. MmCapabilities[CapMirrorEn] needs to be 1 for mirroring. |
| 8 | 0h RW/P | NMCACHING: Near Memory Caching (NMCaching): Enable Near Memory caching, that is, two level memory with the first level (that is, the near memory) having the capability to cache second level memory (that is, far memory). Setting this bit also implies there is a second memory level present. Furthermore, in this implementation, near memory accesses get scheduled by the DDR4 scheduler while the far memory gets serviced by the DDRT scheduler. MmCapabilities[CapNMcachingEn] also needs to be 1 for Near Memory Caching. |
| 7 | 0h RO | Reserved |
| 6 | 0h RW/P | PMEM: Persistent Memory (PMem): Enable persistent memory flows. Furthermore, MmCapabilities[CapPMemEn] needs to be 1 for PMem support. |
| 5 | 0h RW/P | BLOCKREGION: Block Region (BlockRegion): Enable block region memory flows. Furthermore, MmCapabilities[CapBlockRegionEn], Mode[PMem] and MmCapabilities[CapPMemEn] need to be 1 for block region support. |
| 4 | 0h RO | Reserved |
| 3 | 0h RW/P | MEE: Memory Encryption Engine (MEE): Memory Encryption Engine enable. Set this bit to 1 if transactions destined for the Memory Encryption Engine (MEE) might come in. |
| 2 | 0h RW/P | DEDUP: Memory Deduplication Engine (DEDUP) Memory Deduplication Engine enable. Set this bit to 1 if transactions destined for the Memory Deduplication Engine (Dedup) might come in. |
| 1:0 | 0h RO | Reserved |