4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids

Data Sheet Vol. 2 Registers

ID Date Version Classification
814094 12/06/2024 01 Public
Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction Registers Overview Intel® Ultra Path Interconnect (Intel® UPI) Registers Integrated Memory Controller (IMC) Registers Configuration Agent (Ubox) Registers Power Control Unit (PCU) Registers
Legal Disclaimer
Revision History
Introduction
Introduction Related Documents Terminology
Related Documents
Terminology
Registers Overview
Registers Overview Register Spaces and Structure Access Types Configuration Rules Notational Conventions
Register Spaces and Structure
Access Types
Configuration Rules
Notational Conventions
Intel® Ultra Path Interconnect (Intel® UPI) Registers
Intel® Ultra Path Interconnect (Intel® UPI) Registers Bus: B(30), Device: 1-2-3-4, Function: 0 (UPI Misc)
Bus: B(30), Device: 1-2-3-4, Function: 0 (UPI Misc)
Bus: B(30), Device: 1-2-3-4, Function: 0 (UPI Misc) Vendor ID (VID) — Offset 0h Device ID (DID) — Offset 2h PCI Status (PCISTS) — Offset 6h Revision ID and Class Code Register (RID_CCR) — Offset 8h Cache Line Size Register (CLSR) — Offset Ch Header Type (HDR) — Offset Eh Subsystem Vendor ID (SVID) — Offset 2Ch Subsystem ID (SDID) — Offset 2Eh Capability Pointer (CAPPTR) — Offset 34h PCI Express Capability (PXPCAP) — Offset 40h Miscellaneous Clock Control (KTIMISCCLKCTRL) — Offset ECh PCI Express Enhanced Capability (PXPENHCAP) — Offset 100h kti misc privc0 (KTIMISCPRIVC0) — Offset 1D0h kti misc scratch cfg32 (KTIMISCSCRATCHCFG32) — Offset 304h
Vendor ID (VID) — Offset 0h
Device ID (DID) — Offset 2h
PCI Status (PCISTS) — Offset 6h
Revision ID and Class Code Register (RID_CCR) — Offset 8h
Cache Line Size Register (CLSR) — Offset Ch
Header Type (HDR) — Offset Eh
Subsystem Vendor ID (SVID) — Offset 2Ch
Subsystem ID (SDID) — Offset 2Eh
Capability Pointer (CAPPTR) — Offset 34h
PCI Express Capability (PXPCAP) — Offset 40h
Miscellaneous Clock Control (KTIMISCCLKCTRL) — Offset ECh
PCI Express Enhanced Capability (PXPENHCAP) — Offset 100h
kti misc privc0 (KTIMISCPRIVC0) — Offset 1D0h
kti misc scratch cfg32 (KTIMISCSCRATCHCFG32) — Offset 304h
Integrated Memory Controller (IMC) Registers
Integrated Memory Controller (IMC) Registers Bus: B(30), Device: 12, Function: 0 (IMC0 Mesh to Mem Registers)
Bus: B(30), Device: 12, Function: 0 (IMC0 Mesh to Mem Registers)
Bus: B(30), Device: 12, Function: 0 (IMC0 Mesh to Mem Registers) Vendor ID (VID_0_12_0_CFG) — Offset 0h Device ID (DID_0_12_0_CFG) — Offset 2h Header Type (HDR_0_12_0_CFG) — Offset Eh PCI Express Capability (PXPCAP_0_12_0_CFG) — Offset 40h PCI Express Enhanced Capability (PXPENHCAP_0_12_0_CFG) — Offset 100h TAD Read (TAD_RD) — Offset 238h TAD Write (TAD_WR) — Offset 240h Mode register (MODE) — Offset 318h UPI Routing Config (UPIROUTINGCONFIG) — Offset 320h UPI Routing Table (UPIROUTINGTABLE) — Offset 328h
Vendor ID (VID_0_12_0_CFG) — Offset 0h
Device ID (DID_0_12_0_CFG) — Offset 2h
Header Type (HDR_0_12_0_CFG) — Offset Eh
PCI Express Capability (PXPCAP_0_12_0_CFG) — Offset 40h
PCI Express Enhanced Capability (PXPENHCAP_0_12_0_CFG) — Offset 100h
TAD Read (TAD_RD) — Offset 238h
TAD Write (TAD_WR) — Offset 240h
Mode register (MODE) — Offset 318h
UPI Routing Config (UPIROUTINGCONFIG) — Offset 320h
UPI Routing Table (UPIROUTINGTABLE) — Offset 328h
Configuration Agent (Ubox) Registers
Configuration Agent (Ubox) Registers Bus: B(30), Device: 0, Function: 0 (EVNTS) Bus: B(30), Device: 0, Function: 2 (DECS)
Bus: B(30), Device: 0, Function: 0 (EVNTS)
Bus: B(30), Device: 0, Function: 0 (EVNTS) Vendor ID (VID_0_0_0_CFG) — Offset 0h Device ID (DID_0_0_0_CFG) — Offset 2h The register type IntControl_CFG (INTCONTROL_CFG) — Offset 94h The register type CPUNODEID_CFG (CPUNODEID_CFG) — Offset C0h The register type GIDNIDMAP_CFG (GIDNIDMAP_CFG) — Offset D4h
Vendor ID (VID_0_0_0_CFG) — Offset 0h
Device ID (DID_0_0_0_CFG) — Offset 2h
The register type IntControl_CFG (INTCONTROL_CFG) — Offset 94h
The register type CPUNODEID_CFG (CPUNODEID_CFG) — Offset C0h
The register type GIDNIDMAP_CFG (GIDNIDMAP_CFG) — Offset D4h
Bus: B(30), Device: 0, Function: 2 (DECS)
Bus: B(30), Device: 0, Function: 2 (DECS) Vendor ID (VID_0_0_2_CFG) — Offset 0h Device ID (DID_0_0_2_CFG) — Offset 2h The register type CPUBUSNO_CFG (CPUBUSNO_CFG) — Offset D0h SMI generation control (UBOX_SMICTRL_CFG) — Offset D8h
Vendor ID (VID_0_0_2_CFG) — Offset 0h
Device ID (DID_0_0_2_CFG) — Offset 2h
The register type CPUBUSNO_CFG (CPUBUSNO_CFG) — Offset D0h
SMI generation control (UBOX_SMICTRL_CFG) — Offset D8h
Power Control Unit (PCU) Registers
Power Control Unit (PCU) Registers Bus: B(31), Device: 30, Function: 0 (PCU CR0 Registers) Bus: B(31), Device: 30, Function: 2 (PCU CR2 Registers)
Bus: B(31), Device: 30, Function: 0 (PCU CR0 Registers)
Bus: B(31), Device: 30, Function: 0 (PCU CR0 Registers) Vendor ID (VID_1_30_0_CFG) — Offset 0h Device ID (DID_1_30_0_CFG) — Offset 2h PACKAGE ENERGY STATUS (PACKAGE_ENERGY_STATUS_CFG) — Offset 90h PACKAGE TEMPERATURE (PACKAGE_TEMPERATURE_CFG) — Offset C8h TEMPERATURE TARGET (TEMPERATURE_TARGET_CFG) — Offset E4h
Vendor ID (VID_1_30_0_CFG) — Offset 0h
Device ID (DID_1_30_0_CFG) — Offset 2h
PACKAGE ENERGY STATUS (PACKAGE_ENERGY_STATUS_CFG) — Offset 90h
PACKAGE TEMPERATURE (PACKAGE_TEMPERATURE_CFG) — Offset C8h
TEMPERATURE TARGET (TEMPERATURE_TARGET_CFG) — Offset E4h
Bus: B(31), Device: 30, Function: 2 (PCU CR2 Registers)
Bus: B(31), Device: 30, Function: 2 (PCU CR2 Registers) Vendor ID (VID_1_30_2_CFG) — Offset 0h Device ID (DID_1_30_2_CFG) — Offset 2h PCI Command (PCICMD_1_30_2_CFG) — Offset 4h PCI Status (PCISTS_1_30_2_CFG) — Offset 6h Revision ID and Class Code Register (RID_CCR_1_30_2_CFG) — Offset 8h Cache Line Size Register (CLSR_1_30_2_CFG) — Offset Ch PCI Latency Timer (PLAT_1_30_2_CFG) — Offset Dh Header Type (HDR_1_30_2_CFG) — Offset Eh Built In Self Test (BIST_1_30_2_CFG) — Offset Fh Subsystem Vendor ID (SVID_1_30_2_CFG) — Offset 2Ch Subsystem ID (SDID_1_30_2_CFG) — Offset 2Eh Capability Pointer (CAPPTR_1_30_2_CFG) — Offset 34h Interrupt Line (INTL_1_30_2_CFG) — Offset 3Ch Interrupt Pin (INTPIN_1_30_2_CFG) — Offset 3Dh Minimum Grant (MINGNT_1_30_2_CFG) — Offset 3Eh Maximum Latency (MAXLAT_1_30_2_CFG) — Offset 3Fh DRAM ENERGY STATUS (DRAM_ENERGY_STATUS_CFG) — Offset 80h PACKAGE OVERFLOW STATUS (PACKAGE_RAPL_PERF_STATUS) — Offset 88h DRAM POWER INFORMATION (DRAM_POWER_INFO_CFG) — Offset A8h MEM TRML TEMPERATURE REPORT (MEM_TRML_TEMPERATURE_REPORT[0]) — Offset C8h MEM TRML TEMPERATURE REPORT (MEM_TRML_TEMPERATURE_REPORT[1]) — Offset CCh MEM TRML TEMPERATURE REPORT (MEM_TRML_TEMPERATURE_REPORT[2]) — Offset D0h MEM TRML TEMPERATURE REPORT (MEM_TRML_TEMPERATURE_REPORT[3]) — Offset D4h DRAM PLANE OVERFLOW STATUS (DRAM_RAPL_PERF_STATUS_CFG) — Offset D8h THERMTRIP CONFIGURATION (THERMTRIP_CONFIG_CFG) — Offset F8h
Vendor ID (VID_1_30_2_CFG) — Offset 0h
Device ID (DID_1_30_2_CFG) — Offset 2h
PCI Command (PCICMD_1_30_2_CFG) — Offset 4h
PCI Status (PCISTS_1_30_2_CFG) — Offset 6h
Revision ID and Class Code Register (RID_CCR_1_30_2_CFG) — Offset 8h
Cache Line Size Register (CLSR_1_30_2_CFG) — Offset Ch
PCI Latency Timer (PLAT_1_30_2_CFG) — Offset Dh
Header Type (HDR_1_30_2_CFG) — Offset Eh
Built In Self Test (BIST_1_30_2_CFG) — Offset Fh
Subsystem Vendor ID (SVID_1_30_2_CFG) — Offset 2Ch
Subsystem ID (SDID_1_30_2_CFG) — Offset 2Eh
Capability Pointer (CAPPTR_1_30_2_CFG) — Offset 34h
Interrupt Line (INTL_1_30_2_CFG) — Offset 3Ch
Interrupt Pin (INTPIN_1_30_2_CFG) — Offset 3Dh
Minimum Grant (MINGNT_1_30_2_CFG) — Offset 3Eh
Maximum Latency (MAXLAT_1_30_2_CFG) — Offset 3Fh
DRAM ENERGY STATUS (DRAM_ENERGY_STATUS_CFG) — Offset 80h
PACKAGE OVERFLOW STATUS (PACKAGE_RAPL_PERF_STATUS) — Offset 88h
DRAM POWER INFORMATION (DRAM_POWER_INFO_CFG) — Offset A8h
MEM TRML TEMPERATURE REPORT (MEM_TRML_TEMPERATURE_REPORT[0]) — Offset C8h
MEM TRML TEMPERATURE REPORT (MEM_TRML_TEMPERATURE_REPORT[1]) — Offset CCh
MEM TRML TEMPERATURE REPORT (MEM_TRML_TEMPERATURE_REPORT[2]) — Offset D0h
MEM TRML TEMPERATURE REPORT (MEM_TRML_TEMPERATURE_REPORT[3]) — Offset D4h
DRAM PLANE OVERFLOW STATUS (DRAM_RAPL_PERF_STATUS_CFG) — Offset D8h
THERMTRIP CONFIGURATION (THERMTRIP_CONFIG_CFG) — Offset F8h

Power Control Unit (PCU) Registers

The Power Control Unit (PCU) is a dedicated controller that provides power and thermal management for the processor. The PCU implements a PECI interface for out-of-band management. The PCU consists of a dedicated micro-controller, ROM and RAM for Pcode (PCU microcode), HW state machines, I/O registers for interfacing to the microcontroller and interfaces to the hardware units in the processor.

The PCU Registers are implemented in the following Bus, Device, Functions:

  • Bus: B(31), Device: 30, Function: 1 (PCU CR1)
  • Bus: B(31), Device: 30, Function: 2 (PCU CR2)
Note:For additional details on the PCU, see 4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids, Architecture Specification , chapter “Power Controller Unit (PCU) Functional Description.”

Summary of Power Control Unit (PCU) Registers

Bus: B(31), Device: 30, Function: 0 (PCU CR0 Registers)
Bus: B(31), Device: 30, Function: 2 (PCU CR2 Registers)
Bus: B(31), Device: 30, Function: 0 (PCU CR0 Registers)