4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids
Data Sheet Vol. 2 Registers
Register Spaces and Structure
Configuration and Status Registers (CSR)
CSRs are accessed via the configuration transaction mechanism defined in the PCI specification using the Bus, Device, Function number concept to address a specific device's configuration space. All configuration register accesses are accessed over Message Channels through the UBox, but can come from processor cores or via PECI or JTAG interfaces.
Configuration registers can be read or written in byte, WORD (16-bit), or DWORD (32-bit) quantities. Accesses larger than a DWORD to PCI Express configuration space result in unexpected behavior. All multi-byte numeric fields use "little-endian" ordering (lower addresses contain the least significant parts of the field). For a listing of PCI devices with device ID, refer to the Device List Map in the preceding section.
Memory-Mapped I/O (MMIO) Registers
The PCI standard provides CSRs as well as registers which reside in memory-mapped space. For PCI devices, this is typically where the majority of the driver programming occurs and the specific register definitions and characteristics are provided by the device manufacturer. Access to these registers is typically accomplished via CPU reads and writes to non-coherent (UC) or write combining (WC) space. Reads and writes to memory-mapped registers can be accomplished with 1, 2, 4, or 8 byte transactions.
Devices support MMIO space within their IP blocks. This adds support to the Ubox to allow IP blocks to contain MMIO registers that are accessible via the GPSB interface. This permits IP blocks containing MMIO registers to be directly connected (without change) to the internal fabric accessed by proxy through the Ubox.
MMIO Address Space Allocation
Even though BIOS allocates a contiguous 8 MB region to each socket via SAD programming, the Ubox sub-divides this address range into separate BARs. BARs are not relocatable by the operating system.
The Ubox hosted BARs do not follow standard PCIe BAR semantics or address offsets. Having the BARs located outside of the PCIe standard location adds the requirement that BIOS be aware of the location of these registers and will not be determined through device enumeration. BIOS requires access to the MMIO registers across the chip prior to device enumeration.
The following table summarizes the Base Address Register (BAR) for most IP blocks.
| Chapter | Functional Block Registers | BAR |
|---|---|---|
| Accelerators Registers | Intel® DSA | BAR0 |
| Accelerators Registers | Intel® DLB Physical Function | FUNC_BAR |
| Accelerators Registers | Intel® DLB Virtual Function | SRIOV_CAP_FUNC_BAR |
| Host I/O Processor (HIOP) Registers | Intel® VMD | MEMBAR2 |
| Host I/O Processor (HIOP) Registers | Intel® VT-d | VTDBAR |
| Integrated Error Handler (IEH) Registers | Error Logger | SCF BASE |
| I3C* Registers | I3C | SCF BASE |
| Compute Express Link* (CXL*) Cache Memory Controller (CXL.CM) Registers | CXLCM Port Base | EXPPTMBAR |
| Compute Express Link* (CXL*) Cache Memory Controller (CXL.CM) Registers | Port Encryption, RDT | CXLRBBAR |
| Compute Express Link* (CXL*) Cache Memory Controller (CXL.CM) Registers | Bridge to Compute Express Link (B2CXL) | SCF BASE |
| PCI Express* (PCIe*) and CXL IO (CXL.io) Registers | Express Port (EXPPTMBAR) | EXPPTMBAR |
| PCI Express* (PCIe*) and CXL IO (CXL.io) Registers | Integrity Data Encryption (IDE) | KEY_CONFIG_BAR |
| PCI Express* (PCIe*) and CXL IO (CXL.io) Registers | Bridge to High Bandwidth Order Traffic (B2HOT) | SCF BASE |
| Out-Of-Band Management Service Module (OOBMSM) Registers | Management Service Module | PCI_CFG_BAR0 |
| Intel® Trace Hub (Intel® TH) Registers | Intel® Trace Hub | MTB_BAR |
| Secured Startup Services Module (S3M) Registers | ACPI | PWRMBASE |
| Secured Startup Services Module (S3M) Registers | eSPI | SBREG_BAR + CS0/1# |
| Secured Startup Services Module (S3M) Registers | ILMI | SBREG_BAR |
| Secured Startup Services Module (S3M) Registers | SMBus | SMBMBAR |
| Secured Startup Services Module (S3M) Registers | SPI | BIOS_SPI_BAR0 |
| Secured Startup Services Module (S3M) Registers | UART | MEMBAR2 |
| Memory Controller (MC) Registers | Memory Channel (MCCHAN) | SCF BASE |
| DDR Physical Layer (DDRIO) Registers | DDRIO | SCF BASE |
| Memory Security Engine (MSE) Registers | MSE | SCF BASE |
| Caching and Home Agent (CHA) Registers | Bridge to Intra-Die Interconnect (B2IDI) | SCF BASE |
| Configuration Agent (UBOX) Registers | B2UBOX | SCF BASE |
Model Specific Registers (MSRs)
All MSRs are 64-bit and accessed as a Qword quantity through the RDMSR and WRMSR instructions. See the Model Specific Registers (MSRs) chapter in this document for further details.
See also the "Model-Specific Registers" section in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A for more information.