Interrupt Status (INTSTS) – Offset 24 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Interrupt Status (INTSTS) – Offset 24

GIS and CIS bits are not affected by controller reset.

The number of SIS bits in this register is depending on the total number of stream DMA implemented.

Bit Range	Default	Access	Field Name and Description
31	0b	RO/V	Global Interrupt Status (GIS) This bit is an OR of all of the interrupt status bits in this register and PPSTS register
30	0b	RW/V	Controller Interrupt Status (CIS) Status of general controller interrupt. A 1 indicates that an interrupt condition occurred due to a Response Interrupt, a Response Buffer Overrun Interrupt, CORB Memory Error Interrupt, or a SDIN State Change event. The exact cause can be determined by interrogating other registers. Note that a HW interrupt will not be generated unless the corresponding enable bit is set. This bit is an OR of all of the stated interrupt status bits for this register.
29:16	-	-	Reserved
15:0	0h	RW/V	Stream Interrupt Status (SIS) A 1 indicates that an interrupt condition occurred on the corresponding Stream. Note that a HW interrupt will not be generated unless the corresponding enable bit is set. This bit is an OR of all of an individual stream s interrupt status bits. The streams are numbered and the SIS bits assigned sequentially, based on their order in the register set.

Wall Clock Counter (WALCLK)

Interrupt Control (INTCTL) Wall Clock Counter (WALCLK)