Pad Configuration Lock (PADCFGLOCK_DSW_0) – Offset 80 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Pad Configuration Lock (PADCFGLOCK_DSW_0) – Offset 80

Bit Range	Default	Access	Field Name and Description
30:12	-	-	Reserved
11	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_11) Applied to GPD11. Same description as PADCFGLOCK_GPD_0.
10	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_10) Applied to GPD10. Same description as bit 0.
9	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_9) Applied to GPD9. Same description as bit 0.
8	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_8) Applied to GPD8. Same description as bit 0.
7	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_7) Applied to GPD7. Same description as bit 0.
6	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_6) Applied to GPD6. Same description as bit 0.
5	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_5) Applied to GPD5. Same description as bit 0.
4	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_4) Applied to GPD4. Same description as bit 0.
3	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_3) Applied to GPD3. Same description as bit 0.
2	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_2) Applied to GPD2. Same description as bit 0.
1	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_1) Applied to GPD1. Same description as bit 0.
0	0b	RW	Pad Config Lock (PADCFGLOCK_GPD_0) Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. 0 = Unlock 1 = Lock the following register fields as read-only (RO): - Pad Configuration registers (exclude GPIOTXState) - GPI_NMI_EN Register (if implemented) - GPI_SMI_EN Register (if implemented) - GPI_GPE_EN Register (if implemented) When PadCfgLock is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_DSW_0)

Pad Ownership (PAD_OWN_DSW_1) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_DSW_0)