GPIO Serial Blink Enable (GP_SER_BLINK) – Offset 20c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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GPIO Serial Blink Enable (GP_SER_BLINK) – Offset 20c

Bit Range	Default	Access	Field Name and Description
30:5	-	-	Reserved
4:0	00h	RW	GP SER BLINK (GP_SER_BLINK) The setting of this bit has no effect if the corresponding GPIO is programmed as an input, if the corresponding GPIO has the PWM enabled, or if Serial Blink capability does not exist . This bit should be set to a 1 before output buffer is enabled. When set to a '0', the corresponding GPIO will function normally. This bit should be set to a 1 while the corresponding PMode bit is set to 0h (GPIO Mode). Setting the PMode bit to other value (non-GPIO Mode) after the GP_SER_BLINK bit ensures PCH will not drive a 1 on the pin as an output. When this corresponding bit is set to a 1 and the pin is configured to output mode, the serial blink capability is enabled and the programmed message is serialized out through an open-drain buffer configuration. The value of the corresponding GPIOTxState bit remains unchanged and does not impact the serial blink capability in any way. Writes to this register have no effect when the corresponding pin is configured in native mode and the read value returned is undefined. Bit0 = GPP_D0 Bit1 = GPP_D1 Bit2 = GPP_D2 Bit3 = GPP_D3. Bit4 = GPP_D4

Bit Range

Default

Access

Field Name and Description

30:5

Reserved

4:0

00h

GP SER BLINK (GP_SER_BLINK)

The setting of this bit has no effect if the corresponding GPIO is programmed as an input, if the corresponding GPIO has the PWM enabled, or if Serial Blink capability does not exist . This bit should be set to a 1 before output buffer is enabled.

When set to a '0', the corresponding GPIO will function normally.

This bit should be set to a 1 while the corresponding PMode bit is set to 0h (GPIO Mode). Setting the PMode bit to other value (non-GPIO Mode) after the GP_SER_BLINK bit ensures PCH will not drive a 1 on the pin as an output.

When this corresponding bit is set to a 1 and the pin is configured to output mode, the serial blink capability is enabled and the programmed message is serialized out through an open-drain buffer configuration.

The value of the corresponding GPIOTxState bit remains unchanged and does not impact the serial blink capability in any way.

Writes to this register have no effect when the corresponding pin is configured in native mode and the read value returned is undefined.

Bit0 = GPP_D0

Bit1 = GPP_D1

Bit2 = GPP_D2

Bit3 = GPP_D3.

Bit4 = GPP_D4

Family Base Address (FAMBAR)

PWM Control (PWMC) Family Base Address (FAMBAR)