Package C-States

12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
655258	06/15/2023		Public

The processor supports C0, C2, C3, C6, C8, and C10 package states. The following is a summary of the general rules for package C-state entry. These apply to all package C-states, unless specified otherwise:

A package C-state request is determined by the lowest numerical processor IA core C-state amongst all processor IA cores.

A package C-state is automatically resolved by the processor depending on the processor IA core idle power states and the status of the platform components.
- Each processor IA core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C-state.
- The platform may allow additional power savings to be realized in the processor.
- For package C-states, the processor is not required to enter C0 before entering any other C-state.
- Entry into a package C-state may be subject to auto-demotion – that is, the processor may keep the package in a deeper package C-state then requested by the operating system if the processor determines, using heuristics, that the deeper C-state results in better power/performance.

The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following:

If a processor IA core break event is received, the target processor IA core is activated and the break event message is forwarded to the target processor IA core.
- If the break event is not masked, the target processor IA core enters the processor IA core C0 state and the processor enters package C0.
- If the break event is masked, the processor attempts to re-enter its previous package state.

If the break event was due to a memory access or snoop request,
- But the platform did not request to keep the processor in a higher package C-state, the package returns to its previous C-state.
- And the platform requests a higher power C-state, the memory access or snoop request is serviced and the package remains in the higher power C-state.

Package C-State Entry and Exit

PKG C2 and C3 can not be requested explicitly by the software

Package C-States

Package C state	Description	Dependencies
PKG C0	Processor active state. At least one IA core in C0. Processor Graphic in RC0 (Graphics active state) or RC6 (Graphics Core power down state).	-
PKG C2	Cannot be requested explicitly by the Software. All processor IA cores in C6 or deeper + Processor Graphic cores in RC6, memory path may be open. The processor will enter Package C2 when: Transitioning from Package C0 to deep Package C state or from deep Package C state to Package C0. All IA cores requested C6 or deeper + Processor Graphic cores in RC6 but there are constraints (LTR, programmed timer events in the near future and so forth) prevent entry to any state deeper than C2 state. All IA cores requested C6 or deeper + Processor Graphic cores in RC6 but a device memory access request is received. Upon completion of all outstanding memory requests, the processor transitions back into a deeper package C-state.	All processor IA cores in C6 or deeper. Processor Graphic cores in RC6.
PKG C3	Cannot be requested explicitly by the Software. All cores in C6 or deeper + Processor Graphics in RC6, LLC may be flushed and turned off, memory in self refresh, memory clock stopped. The processor will enter Package C3 when: All IA cores in C6 or deeper + Processor Graphic cores in RC6. The platform components/devices allows proper LTR for entering Package C3.	All processor IA cores in C6 or deeper. Processor Graphics in RC6. memory in self refresh, memory clock stopped. LLC may be flushed and turned off.
PKG C6	Package C3 + BCLK is off + IMVP9.1 VRs voltage reduction/PSx state is possible. The processor will enter Package C6 when: All IA cores in C6 or deeper + Processor Graphic cores in RC6. The platform components/devices allow proper LTR for entering Package C6.	Package C3. BCLK is off. IMVP9.1 VRs voltage reduction/PSx state is possible.
PKG C8	Of all IA cores requested C8 + LLC should be flushed at once, voltage will be removed from the LLC. The processor will enter Package C8 when: All IA cores in C8 or deeper + Processor Graphic cores in RC6. The platform components/devices allow proper LTR for entering Package C8.	Package C6 If all IA cores requested C8, LLC is flushed in a single step, voltage will be removed from the LLC.
PKG C10	Package C8 + display in PSR or powered, all VRs at PS4 + crystal clock off. The processor will enter Package C10 when: All IA cores in C10 + Processor Graphic cores in RC6. The platform components/devices allow proper LTR for entering Package C10.	Package C8. All IA cores in C8 or deeper. Display in PSR or powered off¹. All VRs at PS4. Crystal clock off.
Note: Display In PSR is only on single embedded panel configuration and panel support PSR feature.

Package C-State Auto-Demotion

The Processor may demote the Package C-State to a shallower Package C-State to enable better performance, for example instead of going into Package C10, processor will demote to Package C6 (and shallower as required).

The processor's decision to demote the Package C-State is based on Power management parameters such as required C states latencies, entry/exit energy/power, Core wake rates, and device LTR (Latency Tolerance Report). This means that the processor is optimized to minimize platform energy for scenarios with low idle time.

Processor deeper Package C-State entry frequency is controlled to minimize platform energy. When Package C-State Auto-Demotion enabled, a reduced residency in a deeper Package C-State is expected during system runs with high wake rates.

No change at IDLE scenario power consumption due to this feature. Package C-State Auto-Demotion is enabled by default and controlled through BIOS menu.

Modern Standby

Modern Standby is a platform state. On display time out the OS requests the processor to enter package C10 and platform devices at RTD3 (or disabled) in order to attain low power in idle. Modern Standby requires proper BIOS and OS configuration.

Dynamic LLC Sizing

When all processor IA cores request C8 or deeper C-state, internal heuristics dynamically flushes the LLC. Once the processor IA cores enter a deep C-state, depending on their MWAIT sub-state request, the LLC is either gradually flushed N-ways at a time or flushed all at once. Upon the processor IA cores exiting to C0 state, the LLC is gradually expanded based on internal heuristics.