Identification Information

Component Identification via Programming Interface

The processor stepping can be identified by the following register contents:

Table 2-1. U/Y Processor Lines Component Identification

1. The Extended Family, Bits [27:20] are used in conjunction with the Family Code, specified in Bits[11:8], to indicate whether the processor belongs to the Celeron™, Pentium™, or Intel^® Core™ processor family.
2. The Extended Model, Bits [19:16] in conjunction with the Model Number, specified in Bits [7:4], are used to identify the model of the processor within the processor’s family.
3. The Family Code corresponds to Bits [11:8] of the EDX register after RESET, Bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
4. The Model Number corresponds to Bits [7:4] of the EDX register after RESET, Bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.
5. The Stepping ID in Bits [3:0] indicates the revision number of that model. Refer Table 1 for the processor stepping ID number in the CPUID information.
6. When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID value in the EAX register. The EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

Component Marking Information

Figure 2-1. Based on U-Processor Line Multi-Chip Package BGA Top-Side Markings

Pin Count: 1526 Package Size: 50 mm x 25 mm

Production (SSPEC):

• FPO: FPOxxxxx
• {eX}
• SWIR1: Intel^® logoNote:“1” is used to extract the unit visual ID (2D ID).

  Figure 2-2. Based on Y-Processor Line Package BGA Top-Side Markings

  

  Pin Count: 1377 Package Size: 26.5 mm x 18.5 mm

  Production (SSPEC):

  {eX}

  SWIR1: Intel logo

  Note: “1” is used to extract the unit visual ID (2D ID).

  Note:Processor list can be found at: https://ark.intel.com/content/www/us/en/ark/products/codename/74979/ice-lake.html