Problem

Under complex micro-architectural conditions, single step on branches (IA32_​DEBUGCTLMSR (Offset 1D9h, bit [1]) and also TF flag in EFLAGS register is set) in guest might be missed when VMM enables notification on VM Exit (IA32_​VMX_​PROCBASED_​CTLS2 MSR, Offset 48Bh, bit [31]) while the dirty access bit is not set for the code page (bit [6] in paging-structure entry).

Implication

When a single step is enabled under the above condition, some single step branches will be missed. Intel has only observed this erratum in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Intel^® VT-d remapping hardware does perform Reserved(0) check on Page Snoop (PGSNP) field in scalable-mode Process Address ID (PASID) table entry when Snoop Control capability is defined as not available in the Extended Capability Register Offset 10h bit 7 (ECAP.SC=0).

Implication

There are no known functional implications due to this erratum. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the storage subsystem is configured to operate in RAID 0 or 1 mode, a Message Signaled Interrupt (MSI) from an Intel^® Volume Management Device (Intel^® VMD) owned device may interrupt a core before a previous write from the device is completed.

Implication

Due to this erratum, the platform may experience unpredictable system behavior.

Workaround

None identified. The VMD MSI interrupt-handler should initially perform a dummy register read to the MSI initiator device prior to any writes to ensure proper PCIe ordering.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When TC10 is enabled, a USB 3.2 device connected to USB Type-C port directly without retimer may not function as expected.

Implication

Due to this erratum, a USB 3.2 device may not function as expected.

Workaround

None identified. It may be possible for the BIOS to contain a mitigation for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If invalid parameters are provided, the PCONFIG instruction should generate a #GP exception. Due to this erratum, the processor may instead set a ZF flag, with EAX reporting failure reasons.

Implication

Due to this erratum, incorrectly configured PCONFIG usage may lead to unexpected error reporting.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When switching a USB Type-C Display Port (DP) monitor connection between Alt Mode and MFD in S4/S5, the monitor may not be enumerated when resuming from S4/S5.

Implication

Due to this erratum, a DP Monitor may not operate when resuming from S4/S5 and may require a hot plug to recover.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Re-enabling a port following a link disable or hot reset the PCIe Lane Error Status register (Offset 0xA38) may not be cleared.

Implication

Due to this erratum, the Lane Error Status register may indicate lane errors on some of the Root Ports. Intel has not observed any functional issues due this erratum.

Workaround

None identified. Software should ignore the lane error status register to mitigate this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When switching between Type-C Display Alt Mode and a Multi-Function Device (MFD) while the system is in S3/S4/S5, the Display may not enumerate.

Implication

When this erratum occurs, the Display may be blank. A device unplug and re-plug may be necessary to recover the display.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A CALL instruction whose target is the next sequential instruction (the same address pushed onto the stack) will not increment the performance monitoring event BR_​INST_​RETIRED (Event: C4H, UMask: 00H, F9H).

Implication

Due to this erratum, software monitoring Branch Instruction Retired events may undercount. Since the CALL is to the next instruction, control flow tracing with the Last Branch Retired (LBR) records should not be affected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On certain types of branch and complex instructions, the performance monitoring event BR_​INST_​RETIRED (Event: C4H, UMask: 00H / 7EH / BFH / C0H / DFH / EBH / FBH / F9H) will overcount by 1. Affected instructions include FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD, and complex SGX/SMX/CSTATE instructions/flows.

Implication

Due to this erratum, software monitoring Branch Instruction Retired events may overcount.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A Packet Stream Boundary (PSB) packet should be generated for every PSBFreq number of trace output bytes. Due to this erratum, PSB packets may be generated only after as many as four times that number of output bytes have been generated.

Implication

Due to this erratum, trace decoder software may see fewer PSB packets than expected. This may lead to the trace decoder software needing to search further to find a starting point to decode or, when used in circular mode, being unable to decode the trace due to lacking any PSB packets.

Workaround

None identified. The software can request more frequent PSB packets by programming PSBFreq (bits[27:24]) of IA32_​RTIT_​CTL MSR (570H) to a value 1/4 of the desired value.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The act of one processor or system bus master writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross-modifying code (XMC). XMC that does not force the second processor to execute a synchronizing instruction prior to execution of the new code is called unsynchronized XMC.Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code.

Implication

In this case, the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide including a General Protection Fault (GPF) or other unexpected behaviors. In the event that unpredictable execution causes a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system.

Workaround

In order to avoid this erratum programmers should use the XMC synchronization algorithm as detailed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide Section: Handling Self- and Cross-Modifying Code.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events TOPDOWN.BACKEND_​BOUND_​SLOTS (Event A4h, UMask 02h) and IDQ_​BUBBLES.* (Event 9Ch, UMask 01h) may not count when the processor is in the C0.2 power sub-state, which is entered via the TPAUSE or UWAIT instructions. This erratum also impacts the accuracy of MSR_​PERF_​METRICS fields Frontend Bound, Backend Bound, and Fetch Latency (MSR 329h, Bits [23:16], [31:24] and [55:48]).

Implication

Due to this erratum, these performance monitoring events and the fields in MSR_​PERF_​METRICS may be inaccurate.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events IDQ.MS_​UOPS, IDQ.MS_​SWITCHES, and IDQ.MS_​CYCLES_​ANY (Event 79h, UMask 30h) may undercount MS_​UOPS that come from the Decode Stream Buffer (DSB).

Implication

Due to this erratum, performance monitoring counters may report counts lower than expected.

Workaround

None identified. Performance monitoring event UOPS_​RETIRED.MS may be used instead.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring event INT_​VEC_​RETIRED.MUL_​256 (Event E7h, Umask 80h) may not count VPMULLQ instructions.

Implication

Due to this erratum, the performance monitoring event may report lower counts than expected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A VM Exit that occurs while the processor is serving a user interrupt in non-root mode should set the “asynchronous to instruction execution” bit in the Exit Qualification field in the Virtual Machine Control Structure (bit 16). However, if a VM Exit occurs during processing a user interrupt due to an APIC access, the bit will not be set.

Implication

Due to this erratum, the “asynchronous to instruction execution” bit will not be set if an APIC Access VM Exit occurs while the processor is serving a user interrupt. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

PCIe differential reference clocks may go inactive prior to the assertion of PERST#.

Implication

Due to this erratum, the PCI Express^® Card Electromechanical Specification, Revision 5.0, Version 1.0 Power Section 2.2.2 "Management States (S0 to S3/S4 to S0)" requirement is not followed. Intel has not observed any functional implications due to this erratum.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The UC-lock disable feature (MSR_​MEMORY_​CTRL bit [28] (MSR 33h)) may not cause a fault (#AC(4)) for a page split lock that accesses a page with non-WB memory type if the split lock disable (MSR_​MEMORY_​CTRL bit [29]) is not set.

Implication

Due to this erratum, system software may not be able to fully prevent bus locks due to locks to non-WB memory unless they use the split-lock disable feature to prevent bus locks due to splits. Intel has not observed this erratum with any commercially available software.

Workaround

None identified. Software using the UC-lock disable feature should also enable the split lock disable feature.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The PTM Propagation Delay Adaptation Interpretation B (PTMPDAIB) Bit is implemented at Configuration Space (CFG) Offset 158h instead of at 50h as documented in the PCI-SIG PTM Byte Ordering Adaptation Engineering Change Notice (ECN).

Implication

End Point Device (EPD) software that implements the PTM Byte Ordering Adaptation ECN will not be able to program their PTMPDAIB Bit correctly since it is located at a different register offset.

Workaround

None identified. To mitigate this issue, EPD software that implements the PTM Byte Ordering Adaptation ECN must access PTMPDAIB at CFG Offset 158h.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

While in DP2.1 UHBR mode and using the YUV420 format with scaling, displays with a resolution higher than 5K @ 60Hz may show display artifacts.

Implication

Due to this erratum, display artifacts may be seen.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When doing a hotplug on a USB hub with two or more USB Full-speed or Low-speed devices each with a 1 ms service interval interrupt endpoint, a race condition may occur between the PMC and the xHCI controller.

Implication

The processor may fail to enter C3 or deeper package C-States. Note: This erratum has only been observed in a synthetic environment.

Workaround

None identified. This condition is recovered after the xHCI controller has successfully entered D3.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A delay in the availability of LCRD1 (Link Credit 1) from a USB 3.2 hub, with two or more downstream USB 3.2 bulk endpoint devices engaged in SuperSpeedPlus concurrent transfers, may lead to the connected xHCI controller sending the ACK and Status of a transfer packet out of order.

Implication

Due to this erratum, a USB 3.2 bulk endpoint device may not respond to subsequent transfers. It may be possible for a device driver to recover the USB 3.2 device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When Linear Address Masking (LAM) is enabled, a non-canonical fault may be signaled if there is an access which splits the 64-bit linear address space (and thus touches both linear address FFFF_​FFFF_​FFFF_​FFFFh and 0h).

Implication

Due to this erratum, software may receive an unexpected exception on such accesses. Intel has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor accesses to TME exclude range may be encrypted but not decrypted if mapped to remap range.

Implication

Due to this erratum, the processor exclude range it will be encrypted but will but not decrypted if mapped to remap range.

Workaround

It may be possible for BIOS to workaround this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On systems with dual IO mode enabled, SPI0_​IO2 and SPI0_​IO3 may momentarily drive low before these signals are pulled high by internal resistors during boot from the G3 state.

Implication

Due to this erratum, unexpected system behavior may occur on systems when SPI0_​IO2 and SPI0_​IO3 signals are connected to an SPI device.

Workaround

None identified. To mitigate this erratum, do not connect SPI0_​IO2 and SPI0_​IO3 to an SPI device in SPI0 dual IO mode enabled systems.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When reporting a machine check in the module level caches (IA32_​MC1_​STATUS, MSR 405H), a Compound Error Code of type Cache Hierarchy Error will be reported with a Level (LL) Sub-field of 0b10[L2] instead of 0b01[L1].

Implication

Due to this erratum, system software relying on this data, may wrongly categorize the cache level in which the error was reported. The severity of the error will be reported accurately.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

An incorrect Core TLB entry may be retrieved when the retrieval is not completed prior to VM exit.

Implication

Due to this erratum, hypervisor software may read an invalidvalue following VM exit, leading to Windows Bug Check HYPERVISOR_​ERROR (20001h)or SECURE_​KERNEL_​ERROR (18Bh).

Workaround

It may be possible for the BIOS to workaround this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On a system with acoustic noise mitigation Voltage Regulator (VR) Slow Slew Rate (SSR) enabled, the latency values may not be correctly calibrated.

Implication

Due to this erratum , the system may experience lower than expected Deepest Run-time Idle Platform State (DRIPS) leading to a higher than expected power consumption.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Longer than expected processor core power state exit latencies during warm reset or S0ix/S4 flows may delay core wake up.

Implication

Due to this erratum, a system hang with bug check BSOD SYNTHETIC_​WATCHDOG_​TIMEOUT (1CAh), audio glitches, or other unexpected system behavior may occur.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

An incorrect P-core telemetry counter value on package C10 exit may lead to an unexpected core C-State Auto-Demotion.

Implication

Due to this erratum, higher than expected package C0 residency may be observed.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

During an increase in processor frequency, two consecutive RDTSC instructions may return the same value.

Implication

Due to this erratum, software that relies upon the processor monotonically incrementing the time-stamp counter may function incorrectly.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

During PCIe device L0 exit, PCIe Latency Tolerance Reporting (LTR) may not update correctly, resulting in the processor not entering Package State C3 or deeper.

Implication

Due to this erratum, higher than expected power consumption may occur.

Workaround

It may be possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The fields in the IA32_​HWP_​STATUS MSR (Offset 777h, bits [5:2, 0]) which indicate to software that it should change a performance state or frequency, may be cleared following package state C10 exit.

Implication

Due to this erratum, software that relies upon the IA_​32_​HWP_​STATUS MSR may not behave as expected.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, a core may encounter incorrect data when other cores in the system are entering Core C6 or deeper sleep states.

Implication

When this erratum occurs, unpredictable system behavior may be observed. Intel has only observed this behavior in a synthetic test environment.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions involving two or more cores within a module simultaneously entering or exiting Core C6 or deeper sleep states, one or more of those cores may hang without a Machine Check Error being logged.

Implication

Due to this erratum, the system may hang. Intel has only observed this behavior in a synthetic test environment.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the xHCI controller is stressed with concurrent traffic across multiple USB ports, the xHCI controller may fail to service USB 2.0 Isochronous IN endpoints within the required service interval.

Implication

USB 2.0 isochronous devices connected to the xHCI controller may experience dropped packets.Note: This issue has only been observed with a USB 3.2 Bulk Stream device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On USB 3.2 Gen 1x1 only capable ports, including ports configured as USB 3.2 Gen 1x1 by soft strap, the xHCI controller may send only 15 LFPS signals instead of a burst of 16 LFPS signals as specified by the USB 3.2 specification.

Implication

There are no known functional implications due to this erratum. LFPS handshake requires the receiver link partner to only detect 2 LFPS signals. This issue may impact the SuperSpeed compliance test case which checks for the 16 LFPS burst requirements: TD6.4, TD6.5, and TD7.31.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On a system with voltage regulator Slow Slew Rate enabled, the core C1E exit latency values may not be correctly calibrated.

Implication

Due to this erratum, the processor may hang.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A Geyserville transition during power state package C6 exit may result in an incorrect iGFX initialization.

Implication

Due to this erratum, the system may hang with a bug check error VIDEO_​TDR_​FAILURE (0x116).

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a LAN dongle is connected over Type-C USB, the USB Type-C Sub System may not respond on time to the Power Management Controller (PMC) S0ix/S4 sleep request.

Implication

Due to this erratum, the system may perform an unexpected global reset.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller may not send LCRD (Link Credit) to the device after the link U0 state recovery is completed if a USB 3.2 device incorrectly stops sending LCRD.

Implication

When this erratum occurs, subsequence transfers from the device may not be completed and the xHCI host controller driver may initiate a host controller reset.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller may fail to handle a zero-length data packet when doing concurrent traffic with the following devices connected on three separate root ports:

• USB 3.2 Gen 2x1 (or 2x2) hub with at least two USB 3.2 bulk devices.
• USB 3.2 Gen 2x1 (or 2x2) hub with at least two USB 3.2 bulk devices.
• USB isochronous device that sends zero-length data packets.

Implication

Due to this erratum, the xHCI controller may hang. Intel has only observed this behavior with USB audio offload enabled and USB 2.0 audio devices that send zero-length data packets.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the I2S interface is in device mode, the audio controller may not be correctly configured if the audio codec requires high frame polarity.

Implication

Due to this erratum, the left and right audio channels may swap when frame polarity is set to high.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, an indirect branch may jump to a different location than the location expected and reported, leading to the execution of incorrect instructions, while remaining in the current processor mode.

Implication

When this erratum occurs, the execution of incorrect instructions may lead to unpredictable system behavior.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Disconnecting a USB full-speed device from the USB port while the xHCI controller is in the process of sending the Start of Frame may cause the USB 2.0 functionality to become unresponsive for that specific port.

Implication

Due to this erratum, USB 2.0 devices may not be recognized on the USB port until a host controller reset occurs. Intel has only observed this behavior in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When integrated GFX has been disabled in BIOS, the Power Management Sideband (PMSB) may send an unexpected request to a powered down internal Media Engine during Warm Reset/Sx exit.

Implication

Due to this erratum, the system may hang with a Machine Check Exception MSCOD=PMSB_​MESSAGE_​CHANNEL_​TIMEOUT (0081h), MCACOD=UNKNOWN (0414h).

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, following a Core C1 exit, the execution of instructions on a processor core may be blocked.

Implication

Due to this erratum, the system may hang or hang with an Internal Timer Machine Check Exception (IA32_​MCi_​STATUS.MCACOD=400h and IA32_​MCi_​STATUS.MSCOD=E1C4h).

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor may use an incorrect Core logical index table instead of Core physical index table when initiating a Core P0 ratio value read.

Implication

Due to this erratum, the processor may hang. Intel has observed this erratum when using BIOS Mailbox command 0x11 functions, such as override voltage offset for a specific core.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

For Intel^® Core™ Ultra 200HX with pCode versions 4502 or later loaded and for Intel^® Core™ Ultra 200S with pCode versions 5071 or later loaded, the xHCI controller Latency Tolerance Reporting (LTR) values may be incorrectly calibrated.

Implication

Due to this erratum, USB 3.2 isochronous IN devices may experience dropped packets. Intel has observed this issue during video playback on an isochronous camera device.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The Performance Monitoring events, MEM_​BOUND_​STALLS_​LOAD (EventID: 34h) and MEM_​BOUND_​STALLS_​IFETCH (EventID: 35h), and their subevents, will undercount the number of cycles of core initiated requests with latencies that exceed 256 cycles. A CMASK value of 255 may be used to count instances of this erratum.

Implication

Due to this erratum, software monitoring the events for Memory Bound Stalls may undercount.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When software executes Repeat Scan String Byte (REP SCASB) or Repeat Compare String Byte (REP CMPSB) instructions on a core, another core or thread may modify the memory being accessed.

Implication

Due to this erratum, the SCASB or the CMPSB instruction may return incorrect results.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a USB 3.2 device initiates flow control and is connected to the USB Type C* Sub System, the xHCI controller may temporarily pause USB 3.2 bulk transfers until the next micro-frame after the device ends flow control.

Implication

Due to this erratum, USB 3.2 bulk transfers may be temporary paused.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the Intel^® Processor Trace (Intel^® PT) CR3-filtering mechanism is enabled using the CR3Filter bit in IA32_​RTIT_​CTL MSR (MSR 570h, bit 7), CR3 control register bits [63:52] are not compared with the IA32_​RTIT_​CR3_​MATCH MSR (MSR 572h) value.

Implication

Due to this erratum, software that relies upon the IA32_​RTIT_​CTL MSR (bit 7) may function incorrectly.

Workaround

None identified. Software may mitigate this erratum by copying the CR3 register value into IA32_​RTIT_​CR3_​MATCH MSR.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When branch tracing is enabled using branch trace store (BTS) during a task switch, the processor reports the linear address of the branch target in the branch record field "Last Branch from" instead of the linear address of the instruction from which branch was taken.

Implication

Due to this erratum, debug tools relying on BTS may misinterpret control flow.

Workaround

None identified. Software should avoid using BTS to determine the accuracy of branch prediction.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When multiple USB 2.0 split transaction errors occur, the xHCI host controller may become unresponsive.

Implication

Due to this erratum, USB devices connected to the xHCI controller may not function.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring event MEMORY_​ACTIVITY.STALLS_​L2_​MISS (Event 47h, UMASK 05h) may undercount for cases of streaming partial loads.

Implication

Due to this erratum, performance monitoring counters may undercount values for this event and the Top-down Microarchitecture Analysis (TMA) L2_​Bound may be over-estimated for streaming partial loads.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring event MEMORY_​STALLS.L2 (Event 46h, UMASK 02h) may overcount for cases of streaming partial loads.

Implication

Due to this erratum, performance monitoring counters may overcount for this event and the Top-down Microarchitecture Analysis (TMA) L2_​Bound may be over-estimated for streaming partial loads.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The retire latency field in the Timed PEBS (Timed Processor Event Based Sampling) record may report lower retire latency values.

Implication

Due to this erratum, software using the retire latency field for performance analysis may not behave as expected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If a standalone xHCI controller USB port is configured in DbC mode and connected to an external USB 3.2 host controller, it may cause the USB port to go into a non-functional state in the following scenarios:1. The processor exits from S4 or S5, the port may remain in U2.2. The port is connected to a USB 3.2 Gen 1x1 host controller when exiting from S4, S5, or G3, the port may enter into Compliance Mode or an inactive state if Compliance Mode is disabled.3. The port is connected to a USB 3.2 Gen 2x1 host controller when exiting from S4, S5, or G3, the port may enter an inactive state.

Implication

Due to this erratum, the processor standalone xHCI controller USB Type-C port configured in Device Mode (or in DbC mode) may fail to enumerate or become unavailable.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the Intel^® Processor Trace (Intel^® PT) is enabled by setting VM-Entry control field "Load IA32_​RTIT_​CTL" (bit 18) and an event is injected during STM (SMM-transfer monitor) to VMX transition (root or non-root), the following VMCS fields may be incorrect: VM-entry interruption-information field (4016h) VM-entry exception error code (4018h) VM-entry instruction length (401Ah)

Implication

Due to this erratum, the processor may enter HLT state or report an incorrect value in the VMCS IDT-vectoring information field (4408h).

Workaround

A mitigation for this erratum is for software (VMM) to verify the VMCS fields on the next VM exit before executing vmresume.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events BR_​MISP_​RETIRED.COND_​TAKEN_​FWD_​COST and BR_​MISP_​RETIRED.COND_​TAKEN_​BWD_​COST (Event C5h, UMaskExt 80h) may overcount when a branch misprediction happens right after the processor clears speculative instructions.

Implication

Due to this erratum, when PEBS (Processor Event-Based Sampling) is enabled and triggered on an overcount, then the instruction pointer (EventingIP) and retire latency fields may point to the wrong instruction.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under a complex set of microarchitectural conditions, when LBR (Last Branch Record) Event Logging (EN_​LBR_​LOG bit 35 in IA32_​PERFEVTSELx MSR (186h to 18Fh)) is enabled for performance monitoring counters, some event counts may not be logged to PMCx_​CNT fields in IA32_​LBR_​x_​INFO MSR (1200h to 121Fh).

Implication

Due to this erratum, the processor may report incorrect lower values in LBR's record data IA32_​LBR_​x_​INFO.PMCx_​CNT.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller may allocate more bandwidth than can be supported when two or more USB 2.0 periodic devices (Isochronous or Interrupt) are connected behind a USB 3.2 hub.

Implication

Due to this erratum, the xHCI controller may not service the USB 2.0 periodic devices within the required service interval. Intel has only observed missed service intervals when two USB 2.0 Isochronous cameras are connected behind a USB 3.2 Hub and are streaming at 1080p or higher resolution, sometimes resulting in video disruptions on the second camera stream.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the VM-Execution Control "Instruction timeout" (bit 31) is set to 1, and a VM exit occurs with basic exit reason 75 (Instruction timeout) during the delivery of an invalid opcode (#UD) exception, the processor will not set Guest RFLAGS.RF (bit 16).

Implication

When the VMM resumes the guest at the same instruction and an instruction breakpoint is set in the guest, it may trigger double instruction breakpoints (#DB).

Workaround

A mitigation for this erratum is for VMMs to set guest RFLAGS.RF before resuming guest execution following an instruction timeout VM exit.

Status

For the steppings affected, refer to the Summary Table of Changes.