Problem

When the xHCI controller is stressed with concurrent traffic across multiple USB ports, the xHCI controller may fail to service USB 2.0 Isochronous IN endpoints within the required service interval.

Implication

USB 2.0 isochronous devices connected to the xHCI controller may experience dropped packets.Note: This issue has only been observed with a USB 3.2 Bulk Stream device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Intel^® VT-d remapping hardware does perform Reserved(0) check on Page Snoop (PGSNP) field in scalable-mode Process Address ID (PASID) table entry when Snoop Control capability is defined as not available in the Extended Capability Register Offset 10h bit 7 (ECAP.SC=0)

Implication

There are no known functional implications due to this erratum. Intel has not observed this erratum with any commercially available software

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If invalid parameters are provided, the PCONFIG instruction should generate a #GP exception. Due to this erratum, the processor may instead set a ZF flag, with EAX reporting failure reasons.

Implication

Due to this erratum, incorrectly configured PCONFIG usage may lead to unexpected error reporting.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

System software is required to enable scalable mode before programing a device to generate Page Requests. If remapping hardware is programmed to work in legacy-mode or abort-dma-mode receives Page Request, it is expected to generate non-recoverable fault RTA.3 (fault reason 0x32) or RTA.4 (fault reason 0x33) respectively and return a Page Response with status of IR. Due to this erratum remapping hardware will generate the required fault (RTA.3/RTA.4) but not send a Page Response which will result in device waiting forever for the Page Response. This erratum can also be triggered by malicious/buggy device that generates a Page Request even if system software has not enabled it to do so.

Implication

When remapping hardware is not enabled to process Page Requests from a device (i.e. remapping hardware is programmed to work in legacy mode or abort-dma-mode or scalable-mode context entry representing the device has not been programmed to enable Page Requests), a device issuing a Page Request and waiting for Page Responses will wait indefinitely leading to a hang.

Workaround

None identified. Most modern system softwares do not violate architecture specification. Therefore, Intel has not encountered this failure on a real system. System software should plan on performing Functional Level Reset on malicious/buggy device that causes RTA.3/RTA.4 fault and if necessary, remove such device from platform.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller may not send LCRD (Link Credit) to the device after the link U0 state recovery is completed if a USB 3.2 device incorrectly stops sending LCRD.

Implication

When this erratum occurs, subsequence transfers from the device may not be completed and the xHCI host controller driver may initiate a host controller reset.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Problem: When switching between Type-C Display Alt Mode and a Multi-Function Device (MFD) while the system is in S3/S4/S5, the Display may not enumerate.

Implication

When this erratum occurs, the Display may be blank. A device unplug and re-plug may be necessary to recover the display.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A CALL instruction whose target is the next sequential instruction (the same address pushed onto the stack) will not increment the performance monitoring event BR_​INST_​RETIRED (Event: C4H, UMask: 00H, F9H).

Implication

Due to this erratum, software monitoring Branch Instruction Retired events may undercount. Since the CALL is to the next instruction, control flow tracing with the Last Branch Retired (LBR) records should not be affected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On certain types of branch and complex instructions the performance monitoring event BR_​INST_​RETIRED (Event: C4H, UMask: 00H / 7EH / BFH / C0H / DFH / EBH / FBH / F9H) will overcount by 1. Affected instructions include FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD and complex SGX/SMX/CSTATE instructions/flows.

Implication

Due to this erratum, software monitoring Branch Instruction Retired events may overcount.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A Packet Stream Boundary (PSB) packet should be generated for every PSBFreq number of trace output bytes. Due to this erratum, PSB packets may be generated only after as many as four times that number of output bytes have been generated.

Implication

Due to this erratum, trace decoder software may see fewer PSB packets than expected. This may lead to the trace decoder software needing to search further to find a starting point to decode or, when used in circular mode, being unable to decode the trace due to lacking any PSB packets.

Workaround

None identified. Software can request more frequent PSB packets by programming PSBFreq (bits [27:24]) of IA32_​RTIT_​CTL MSR (570H) to a value 1/4 of the desired value.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The act of one processor or system bus master writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross-modifying code (XMC). XMC that does not force the second processor to execute a synchronizing instruction prior to execution of the new code is called unsynchronized XMC.Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code.

Implication

In this case the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide including a General Protection Fault (GPF) or other unexpected behaviors. In the event that unpredictable execution causes a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system.

Workaround

In order to avoid this erratum programmers should use the XMC synchronization algorithm as detailed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide Section: Handling Self- and Cross-Modifying Code.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events TOPDOWN.BACKEND_​BOUND_​SLOTS (Event A4h, UMask 02h) and IDQ_​BUBBLES.* (Event 9Ch, UMask 01h) may not count when the processor is in the C0.2 power sub-state, which is entered via the TPAUSE or UWAIT instructions. This erratum also impacts the accuracy of MSR_​PERF_​METRICS fields Frontend Bound, Backend Bound, and Fetch Latency (MSR 329h, Bits [23:16], [31:24] and [55:48]).

Implication

Due to this erratum, these performance monitoring events and the fields in MSR_​PERF_​METRICS may be inaccurate.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events IDQ.MS_​UOPS, IDQ.MS_​SWITCHES, and IDQ.MS_​CYCLES_​ANY (Event 79h, UMask 30h) may undercount MS_​UOPS that come from the Decode Stream Buffer (DSB).

Implication

Due to this erratum, performance monitoring counters may report counts lower than expected.

Workaround

None identified. Performance monitoring event UOPS_​RETIRED.MS may be used instead.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring event INT_​VEC_​RETIRED.MUL_​256 (Event E7h, Umask 80h) may not count VPMULLQ instructions.

Implication

Due to this erratum, the performance monitoring event may report lower counts than expected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor accesses to TME exclude range may be encrypted but not decrypted if mapped to remap range.

Implication

Due to this erratum, the processor exclude range it will be encrypted but will but not decrypted if mapped to remap range.

Workaround

It may be possible for BIOS to workaround this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Disconnecting a USB full-speed device from the USB port while the xHCI controller is in the process of sending the Start of Frame may cause the USB 2.0 functionality to become unresponsive for that specific port.

Implication

Due to this erratum, USB 2.0 devices may not be recognized on the USB port until a host controller reset occurs. Intel has only observed this behavior in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the Multiple Message Capable field (bits [17:19]) is set to '0' in the NPU MSI Capability register (Bus 0; Device 11; Function 0; Offset D0h), the NPU MSI Pending register (Bus 0; Device 11; Function 0; Offset E4h) may incorrectly show a single pending interrupt vector in one of bits [1:25] rather than in bit 0 as expected.

Implication

Due to this erratum, software that relies upon processing the NPU MSI Pending register may not behave as expected. Intel has not observed this erratum to impact any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When doing a hotplug on a USB hub with two or more USB Full-speed or Low-speed devices each with a 1 ms service interval interrupt endpoint, a race condition may occur between the PMC and the xHCI controller.

Implication

The processor may fail to enter C3 or deeper package C-States. Note: This erratum has only been observed in a synthetic environment.

Workaround

None identified. This condition is recovered after the xHCI controller has successfully entered D3.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On USB 3.2 Gen 1x1 only capable ports, including ports configured as USB 3.2 Gen 1x1 by soft strap, the xHCI controller may send only 15 LFPS signals instead of a burst of 16 LFPS signals as specified by the USB 3.2 specification.

Implication

There are no known functional implications due to this erratum. LFPS handshake requires the receiver link partner to only detect 2 LFPS signals. This issue may impact the SuperSpeed compliance test case which checks for the 16 LFPS burst requirements: TD6.4, TD6.5, and TD7.31.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A delay in the availability of LCRD1 (Link Credit 1) from a USB 3.2 hub, with two or more downstream USB 3.2 bulk endpoint devices engaged in SuperSpeedPlus concurrent transfers, may lead to the connected xHCI controller sending the ACK and Status of a transfer packet out of order.

Implication

Due to this erratum, a USB 3.2 bulk endpoint device may not respond to subsequent transfers. It may be possible for a device driver to recover the USB 3.2 device.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Workloads utilizing Graphics Memory Bandwidth Compression may cause unexpected Graphics behavior.

Implication

Due to this erratum, graphics visual or data artifacts may occur, which may lead to Timeout Detection and Recovery (TDR) or application crash.

Workaround

None identified. A mitigation is available in Intel GFX driver Rev 101.5637 that disable Graphics compression in identified affected.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

An unexpected Global Reset may occur when performing a microcode update with an invalid MCU.

Implication

Due to this erratum, software performing the microcode update may not function as expected.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The Intel^® HD Audio Controller may behave abnormally with frequent starts and stops of audio playback over a short period of time.

Implication

Due to this erratum, the Intel^® HD Audio Controller may cause the system to hang.

Workaround

A fix has been identified for this erratum and may be available in a software update.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On systems with dual IO mode enabled, SPI0_​IO2 and SPI0_​IO3 may momentarily drive low before these signals are pulled high by internal resistors during boot from the G3 state.

Implication

Due to this erratum, unexpected system behavior may occur on systems when SPI0_​IO2 and SPI0_​IO3 signals are connected to an SPI device.

Workaround

None identified. To mitigate this erratum, do not connect SPI0_​IO2 and SPI0_​IO3 to an SPI device in SPI0 dual IO mode enabled systems.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

While in DP2.1 UHBR mode and using the YUV420 format with scaling, displays with a resolution higher than 5K @ 60Hz may show display artifacts.

Implication

Due to this erratum, display artifacts may be seen.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The UC-lock disable feature (MSR_​MEMORY_​CTRL bit [28] (MSR 33h)) may not cause a fault (#AC(4)) for a page split lock that accesses a page with non-WB memory type if the split lock disable (MSR_​MEMORY_​CTRL bit [29]) is not set.

Implication

Due to this erratum, system software may not be able to fully prevent bus locks due to locks to non-WB memory unless they use the split-lock disable feature to prevent bus locks due to splits. Intel has not observed this erratum with any commercially available software.

Workaround

None identified. Software using the UC-lock disable feature should also enable the split lock disable feature.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

While running concurrent workloads on the VPU, PCIe Device10, and the GT/Media engine, the GT/Media engine may hang while entering RC6/MC6.

Implication

Due to this erratum, a Video Timeout Detection and Recovery (TDR) BSOD 0x116 or a Graphics HYPERVISOR_​ERROR error may occur, leading to a system hang.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When TC10 is enabled, a USB 3.2 device connected to USB Type-C port directly without retimer may not function as expected.

Implication

Due to this erratum, a USB 3.2 device may not function as expected.

Workaround

None identified. It may be possible for the BIOS to contain a mitigation for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

P-cores may not exit power state Core C6 on monitor hit

Implication

Due to this erratum, software may exhibit delayed responsiveness. Software using interrupt-based wakeups is not impacted.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a USB 3.2 device is connected and the link enters U3, the xHCI USB 3.2 PHY may turn off the Rx termination during U3 link exit.

Implication

Due to this erratum, the USB 3.2 device may re-enumerate after exiting the U3 link state.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When reporting a machine check in the module level caches (IA32_​MC1_​STATUS, MSR 405H), a Compound Error Code of type Cache Hierarchy Error will be reported with a Level (LL) Sub-field of 0b10[L2] instead of 0b01[L1].

Implication

Due to this erratum, system software relying on this data, may wrongly categorize the cache level in which the error was reported. The severity of the error will be reported accurately.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

An incorrect Core TLB entry may be retrieved when the retrieval is not completed prior to VM exit.

Implication

Due to this erratum, hypervisor software may read an invalidvalue following VM exit, leading to Windows Bug Check HYPERVISOR_​ERROR (20001h)or SECURE_​KERNEL_​ERROR (18Bh).

Workaround

It may be possible for the BIOS to contain a workaround this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitecture scenarios processor internal register access may not respond in time leading to pCode internal timeout.

Implication

Due to this erratum, a system running pCode versions 2.6.10 may observe unexpected global reset or may hang with a PCODE_​INTERNAL_​ERROR Machine Check (IA32_​MCi_​STATUS.MCACOD=0410H and MSCOD=0003H).

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Sx/S0ix entry power down sequence may not operate as expected due to an incorrect handshake flow.

Implication

Due to this erratum, the system may hang with a Machine Check Error MSCOD=PCU_​MCA_​MSEC_​HWERR (0814H), MCACOD=PUNIT_​INTERNAL_​ERROR (0402H).

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Processor SRAM transactions may not complete as expected when also using concurrent PCIe telemetry (Bus: 0 ; Device: 10; Function: 0).

Implication

Due to this erratum, unpredictable system behavior may occur.

Workaround

A fix has been identified for this erratum and may be available in a software update.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

During an increase in processor frequency, two consecutive RDTSC instructions may return the same value.

Implication

Due to this erratum, software that relies upon the processor monotonically incrementing the time-stamp counter may function incorrectly.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Following a VR Thermal event, the processor may not send a getreg command to PMIC fixed SVID voltage regulators (VCCDDRIO And VCCAONL) that is required by PMIC to de-assert the alert signal.

Implication

Due to this erratum, a processor alert signal de-assertion may be delayed which may add unexpected latency to power management package C exit, resulting in behavior such as screen flickers or screen artifacts.

Workaround

It may be possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor's DDR thermal controller may not behave as expected when the DRAM temperature is equal to or exceeds the maximum temperature threshold (DDR_​THERM_​CONTROL_​0_​0_​0_​MCHBAR_​PCU Offset 5e88h bits[7:0])

Implication

Due to this erratum, the processor may throttle and continue to throttle the memory sub system and other processor domains.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The fields in the IA32_​HWP_​STATUS MSR (Offset 777h, bits [5:2, 0]) which indicate to software that it should change a performance state or frequency, may be cleared following package state C10 exit.

Implication

Due to this erratum, software that relies upon the IA_​32_​HWP_​STATUS MSR may not behave as expected.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, a core may encounter incorrect data when other cores in the system are entering Core C6 or deeper sleep states.

Implication

When this erratum occurs, unpredictable system behavior may be observed. Intel has only observed this behavior in a synthetic test environment.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions involving two or more cores within a module simultaneously entering or exiting Core C6 or deeper sleep states, one or more of those cores may hang without a Machine Check Error being logged.

Implication

Due to this erratum, the system may hang. Intel has only observed this behavior in a synthetic test environment.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, an indirect branch may jump to a different location than the location expected and reported, leading to the execution of incorrect instructions, while remaining in the current processor mode.

Implication

When this erratum occurs, the execution of incorrect instructions may lead to unpredictable system behavior.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, following a Core C1 exit, the execution of instructions on a processor core may be blocked.

Implication

Due to this erratum, the system may hang or hang with an Internal Timer Machine Check Exception (IA32_​MCi_​STATUS.MCACOD=400h and IA32_​MCi_​STATUS.MSCOD=E1C4h).

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When software executes Repeat Scan String Byte (REP SCASB) or Repeat Compare String Byte (REP CMPSB) instructions on a core, another core or thread may modify the memory being accessed.

Implication

Due to this erratum, the SCASB or the CMPSB instruction may return incorrect results.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The Performance Monitoring events, MEM_​BOUND_​STALLS_​LOAD (EventID: 34h) and MEM_​BOUND_​STALLS_​IFETCH (EventID: 35h), and their subevents, will undercount the number of cycles of core initiated requests with latencies that exceed 256 cycles. A CMASK value of 255 may be used to count instances of this erratum.

Implication

Due to this erratum, software monitoring the events for Memory Bound Stalls may undercount.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When there is concurrent USB 2.0 Isochronous IN and USB 3.2 Bulk traffic on the standalone xHCI controller, the USB 2.0 Isochronous device may not be serviced within the required service interval if the processor enters package C-State C6 or deeper state.

Implication

Due to this erratum, USB 2.0 isochronous IN devices may experience dropped packets. This issue has only been observed when using a USB 3.2 Bulk device that initiates frequent flow control.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a USB 3.2 device initiates flow control and is connected to the USB Type C* Sub System, the xHCI controller may temporarily pause USB 3.2 bulk transfers until the next micro-frame after the device ends flow control.

Implication

Due to this erratum, USB 3.2 bulk transfers may be temporary paused.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the Intel^® Processor Trace (Intel^® PT) CR3-filtering mechanism is enabled using the CR3Filter bit in IA32_​RTIT_​CTL MSR (MSR 570h, bit 7), CR3 control register bits [63:52] are not compared with the IA32_​RTIT_​CR3_​MATCH MSR (MSR 572h) value.

Implication

Due to this erratum, software that relies upon the IA32_​RTIT_​CTL MSR (bit 7) may function incorrectly.

Workaround

None identified. Software may mitigate this erratum by copying the CR3 register value into IA32_​RTIT_​CR3_​MATCH MSR.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When branch tracing is enabled using branch trace store (BTS) during a task switch, the processor reports the linear address of the branch target in the branch record field "Last Branch from" instead of the linear address of the instruction from which branch was taken.

Implication

Due to this erratum, debug tools relying on BTS may misinterpret control flow.

Workaround

None identified. Software should avoid using BTS to determine the accuracy of branch prediction.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When multiple USB 2.0 split transaction errors occur, the xHCI host controller may become unresponsive.

Implication

Due to this erratum, USB devices connected to the xHCI controller may not function.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring event MEMORY_​ACTIVITY.STALLS_​L2_​MISS (Event 47h, UMASK 05h) may undercount for cases of streaming partial loads.

Implication

Due to this erratum, performance monitoring counters may undercount values for this event and the Top-down Microarchitecture Analysis (TMA) L2_​Bound may be over-estimated for streaming partial loads.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring event MEMORY_​STALLS.L2 (Event 46h, UMASK 02h) may overcount for cases of streaming partial loads.

Implication

Due to this erratum, performance monitoring counters may overcount for this event and the Top-down Microarchitecture Analysis (TMA) L2_​Bound may be over-estimated for streaming partial loads.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The retire latency field in the Timed PEBS (Timed Processor Event Based Sampling) record may report lower retire latency values.

Implication

Due to this erratum, software using the retire latency field for performance analysis may not behave as expected.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Remapping hardware does not perform Reserved(0) check on b[127:HAW+64] of the Interrupt Remap Table Entry for a Posted Interrupt.

Implication

Due to this erratum, system software violating VT-d architecture requirement by programming non-zero reserved values in b[127:HAW+64] of Interrupt Remap Table entry for Posted Interrupt may not fault on current processors but may fault on future processors. Intel has not observed this sighting/erratum with any commercially available system.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If a standalone xHCI controller USB port is configured in DbC mode and connected to an external USB 3.2 host controller, it may cause the USB port to go into a non-functional state in the following scenarios:1. The processor exits from S4 or S5, the port may remain in U2.2. The port is connected to a USB 3.2 Gen 1x1 host controller when exiting from S4, S5, or G3, the port may enter into Compliance Mode or an inactive state if Compliance Mode is disabled.3. The port is connected to a USB 3.2 Gen 2x1 host controller when exiting from S4, S5, or G3, the port may enter an inactive state.

Implication

Due to this erratum, the processor standalone xHCI controller USB Type-C port configured in Device Mode (or in DbC mode) may fail to enumerate or become unavailable.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the Intel^® Processor Trace (Intel^® PT) is enabled by setting VM-Entry control field "Load IA32_​RTIT_​CTL" (bit 18) and an event is injected during STM (SMM-transfer monitor) to VMX transition (root or non-root), the following VMCS fields may be incorrect: VM-entry interruption-information field (4016h) VM-entry exception error code (4018h) VM-entry instruction length (401Ah)

Implication

Due to this erratum, the processor may enter HLT state or report an incorrect value in the VMCS IDT-vectoring information field (4408h).

Workaround

A mitigation for this erratum is for software (VMM) to verify the VMCS fields on the next VM exit before executing vmresume.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events BR_​MISP_​RETIRED.COND_​TAKEN_​FWD_​COST and BR_​MISP_​RETIRED.COND_​TAKEN_​BWD_​COST (Event C5h, UMaskExt 80h) may overcount when a branch misprediction happens right after the processor clears speculative instructions.

Implication

Due to this erratum, when PEBS (Processor Event-Based Sampling) is enabled and triggered on an overcount, then the instruction pointer (EventingIP) and retire latency fields may point to the wrong instruction.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under a complex set of microarchitectural conditions, when LBR (Last Branch Record) Event Logging (EN_​LBR_​LOG bit 35 in IA32_​PERFEVTSELx MSR (186h to 18Fh)) is enabled for performance monitoring counters, some event counts may not be logged to PMCx_​CNT fields in IA32_​LBR_​x_​INFO MSR (1200h to 121Fh).

Implication

Due to this erratum, the processor may report incorrect lower values in LBR's record data IA32_​LBR_​x_​INFO.PMCx_​CNT.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller may allocate more bandwidth than can be supported when two or more USB 2.0 periodic devices (Isochronous or Interrupt) are connected behind a USB 3.2 hub.

Implication

Due to this erratum, the xHCI controller may not service the USB 2.0 periodic devices within the required service interval. Intel has only observed missed service intervals when two USB 2.0 Isochronous cameras are connected behind a USB 3.2 Hub and are streaming at 1080p or higher resolution, sometimes resulting in video disruptions on the second camera stream.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the VM-Execution Control "Instruction timeout" (bit 31) is set to 1, and a VM exit occurs with basic exit reason 75 (Instruction timeout) during the delivery of an invalid opcode (#UD) exception, the processor will not set Guest RFLAGS.RF (bit 16).

Implication

When the VMM resumes the guest at the same instruction and an instruction breakpoint is set in the guest, it may trigger double instruction breakpoints (#DB).

Workaround

A mitigation for this erratum is for VMMs to set guest RFLAGS.RF before resuming guest execution following an instruction timeout VM exit.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If a MOV SS or POP SS instruction generated a debug exception, and is not followed by an explicit write to the stack pointer (SP), the processor may fail to deliver the debug exception or, if it does, the DR6 register contents may not correctly reflect the causes of the debug exception.

Implication

Debugging software may fail to operate properly if a debug exception is lost or does not report complete information. Intel has not observed this erratum with any commercially available software.

Workaround

Software should explicitly write to the stack pointer immediately after executing MOV SS or POP SS.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The following clock timing specifications of Serial IO and Integrated Sensor Hub (ISH) I3C interfaces may not meet the minimum timing requirements listed in the MIPI specification version 1.0:• Serial IO and ISH: SCL and SDA fall time when operating in I2C mode for Fast Mode (400 Kbps) and Fast Mode Plus (1 Mbps) speeds. • Serial IO and ISH: SCL rise time when operating in I2C mode for Fast Mode (400 Kbps). • Serial IO: SCL low time when operating in I2C mode for Fast Mode (400 Kbps) and Fast Mode Plus (1 Mbps) speeds.

Implication

There are no known functional implications due to this erratum and Intel has not observed this erratum with any commercially available system.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When “virtualize APIC accesses” and “IPI virtualization” are both 1, and both “virtual‑interrupt delivery” and “APIC‑register virtualization” are 0, a memory‑mapped read of the Interrupt Command Register (ICR) may return data from the virtual‑APIC page (VICR) instead of generating an APIC‑access VM exit.

Implication

Due to this erratum, software that relies on an APIC-access VM exit for ICR reads may function incorrectly.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When an Intel^® In-Memory Analytics Accelerator (IAA) device decompress operation has a non-zero Source 1 Size, and if the sum of Drop Initial Bits of Analytics Engine Configuration and State (AECS; offset 1DCh) and Ignore End Bits (Decompression Flags, bits [8:6]) is equal to Source 1 Size times 8, the operation correctly drops all the Source 1 data. However, if the operation also results in a recoverable output buffer overflow (Completion Record Status Code 0Bh), then the value of Bytes Completed in the Completion Record (bytes 4 to 7) or the value of Drop Initial Bits field in the AECS may be incorrect.

Implication

Due to this erratum, the incorrect values may lead to the subsequent decompress operation, that is, the continuation of the same job producing an incorrect result.

Workaround

None identified. It is possible for software to contain a workaround for this issue.

Status

For the steppings affected, refer to the Summary Table of Changes.