13th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S/P/PX/H/HX/U Processor Line Platforms, formerly known as Raptor Lake

Download as PDF
ID 743844
Date 06/15/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction Technologies Power Management Thermal Management Memory USB-C* Sub System PCIe* Interface Direct Media Interface and On Package Interface Graphics Display Camera/MIPI Signal Description Electrical Specifications Package Mechanical Specifications CPU And Device IDs
Legal Disclaimer
Revision History
Introduction
Introduction Processor Volatility Statement Package Support Supported Technologies Power Management Support Thermal Management Support Ball-out Information Processor Testability Operating Systems Support Terminology and Special Marks Related Documents
Processor Volatility Statement
Package Support
Supported Technologies
Supported Technologies API Support (Windows*)
API Support (Windows*)
Power Management Support
Power Management Support Processor Core Power Management System Power Management Memory Controller Power Management Processor Graphics Power Management
Processor Core Power Management
System Power Management
Memory Controller Power Management
Processor Graphics Power Management
Thermal Management Support
Ball-out Information
Processor Testability
Operating Systems Support
Terminology and Special Marks
Related Documents
Technologies
Technologies Platform Environmental Control Interface Intel® Virtualization Technology Security Technologies Power and Performance Technologies Intel® Image Processing Unit Debug Technologies Clock Topology Intel Volume Management Device Technology Deprecated Technologies
Platform Environmental Control Interface
Platform Environmental Control Interface PECI Bus Architecture
PECI Bus Architecture
Intel® Virtualization Technology
Intel® Virtualization Technology Intel® VT for Intel® 64 and Intel® Architecture Intel® Virtualization Technology for Directed I/O Intel® APIC Virtualization Technology (Intel® APICv) Hypervisor-Managed Linear Address Translation
Intel® VT for Intel® 64 and Intel® Architecture
Intel® Virtualization Technology for Directed I/O
Intel® APIC Virtualization Technology (Intel® APICv)
Hypervisor-Managed Linear Address Translation
Security Technologies
Security Technologies Intel® Trusted Execution Technology Intel® Advanced Encryption Standard New Instructions Perform Carry-Less Multiplication Quad Word Instruction Intel® Secure Key Execute Disable Bit Boot Guard Technology Intel® Supervisor Mode Execution Protection Intel® Supervisor Mode Access Protection Intel® Secure Hash Algorithm Extensions User Mode Instruction Prevention Read Processor ID Intel® Total Memory Encryption - Multi-Key Intel® Control-flow Enforcement Technology KeyLocker Technology Devil’s Gate Rock
Intel® Trusted Execution Technology
Intel® Advanced Encryption Standard New Instructions
Perform Carry-Less Multiplication Quad Word Instruction
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection
Intel® Supervisor Mode Access Protection
Intel® Secure Hash Algorithm Extensions
User Mode Instruction Prevention
Read Processor ID
Intel® Total Memory Encryption - Multi-Key
Intel® Control-flow Enforcement Technology
Intel® Control-flow Enforcement Technology Shadow Stack Indirect Branch Tracking
Shadow Stack
Indirect Branch Tracking
KeyLocker Technology
Devil’s Gate Rock
Power and Performance Technologies
Power and Performance Technologies Intel® Smart Cache Technology IA Cores Level 1 and Level 2 Caches Ring Interconnect Intel® Performance Hybrid Architecture Intel® Turbo Boost Max Technology 3.0 Power Aware Interrupt Routing (PAIR) Intel® Hyper-Threading Technology Intel® Turbo Boost Technology 2.0 Enhanced Intel SpeedStep® Technology Intel® Thermal Velocity Boost (Intel® TVB) Intel® Speed Shift Technology Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® 64 Architecture x2APIC Intel® Dynamic Tuning Technology Intel® GMM and Neural Network Accelerator Cache Line Write Back Remote Action Request User Mode Wait Instructions Intel® Adaptive Boost Technology
Intel® Smart Cache Technology
IA Cores Level 1 and Level 2 Caches
Ring Interconnect
Intel® Performance Hybrid Architecture
Intel® Turbo Boost Max Technology 3.0
Power Aware Interrupt Routing (PAIR)
Intel® Hyper-Threading Technology
Intel® Turbo Boost Technology 2.0
Intel® Turbo Boost Technology 2.0 Intel® Turbo Boost Technology 2.0 Frequency Intel® Turbo Boost Technology 2.0 Power Control Intel® Turbo Boost Technology 2.0 Power Monitoring
Intel® Turbo Boost Technology 2.0 Frequency
Intel® Turbo Boost Technology 2.0 Power Control
Intel® Turbo Boost Technology 2.0 Power Monitoring
Enhanced Intel SpeedStep® Technology
Intel® Thermal Velocity Boost (Intel® TVB)
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® AVX2 Vector Neural Network Instructions (AVX2 VNNI)
Intel® AVX2 Vector Neural Network Instructions (AVX2 VNNI)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology
Intel® GMM and Neural Network Accelerator
Cache Line Write Back
Remote Action Request
User Mode Wait Instructions
Intel® Adaptive Boost Technology
Intel® Image Processing Unit
Platform Imaging Infrastructure Intel® Image Processing Unit
Platform Imaging Infrastructure
Intel® Image Processing Unit
Debug Technologies
Debug Technologies Intel® Processor Trace Platform CrashLog Telemetry Aggregator
Intel® Processor Trace
Platform CrashLog
Telemetry Aggregator
Clock Topology
Clock Topology Integrated Reference Clock PLL
Integrated Reference Clock PLL
Intel Volume Management Device Technology
Deprecated Technologies
Power Management
Power Management Advanced Configuration and Power Interface (ACPI) States Supported Processor IA Core Power Management Processor AUX Power Management Processor Graphics Power Management System Agent Enhanced Intel SpeedStep® Technology Rest Of Platform (ROP) PMIC PCI Express* Power Management TCSS Power State
Advanced Configuration and Power Interface (ACPI) States Supported
Processor IA Core Power Management
Processor IA Core Power Management OS/HW Controlled P-states Low-Power Idle States Requesting the Low-Power Idle States Processor IA Core C-State Rules Package C-States Package C-States and Display Resolutions
OS/HW Controlled P-states
Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Low-Power Idle States
Requesting the Low-Power Idle States
Processor IA Core C-State Rules
Package C-States
Package C-States and Display Resolutions
Processor AUX Power Management
Processor Graphics Power Management
Processor Graphics Power Management Memory Power Savings Technologies Display Power Savings Technologies Processor Graphics Core Power Savings Technologies
Memory Power Savings Technologies
Display Power Savings Technologies
Processor Graphics Core Power Savings Technologies
System Agent Enhanced Intel SpeedStep® Technology
Rest Of Platform (ROP) PMIC
PCI Express* Power Management
TCSS Power State
Thermal Management
Thermal Management Processor Thermal Management General Notes Processor Line Power and Frequency Specifications Processor Line Thermal and Power Specifications
Processor Thermal Management
Processor Thermal Management Thermal Considerations Assured Power (cTDP) Thermal Management Features Intel® Memory Thermal Management
Thermal Considerations
Thermal Considerations Package Power Control Platform Power Control Turbo Time Parameter (Tau)
Package Power Control
Platform Power Control
Turbo Time Parameter (Tau)
Assured Power (cTDP)
Assured Power (cTDP) Assured Power (cTDP)
Assured Power (cTDP)
Thermal Management Features
Thermal Management Features Adaptive Thermal Monitor Digital Thermal Sensor PROCHOT# Signal PROCHOT Output Only Bi-Directional PROCHOT# PROCHOT Demotion Algorithm Voltage Regulator Protection using PROCHOT# Thermal Solution Design and PROCHOT# Behavior Low-Power States and PROCHOT# Behavior THRMTRIP# Signal Critical Temperature Detection On-Demand Mode MSR Based On-Demand Mode I/O Emulation-Based On-Demand Mode
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
On-Demand Mode
MSR Based On-Demand Mode
I/O Emulation-Based On-Demand Mode
Intel® Memory Thermal Management
General Notes
Processor Line Power and Frequency Specifications
Processor Line Thermal and Power Specifications
Memory
Memory System Memory Interface Integrated Memory Controller (IMC) Power Management
System Memory Interface
System Memory Interface Processor SKU Support Matrix Supported Memory Modules and Devices System Memory Timing Support Memory Controller (MC) Memory Controller Power Gate System Memory Controller Organization Mode (DDR4/5 Only) System Memory Frequency Technology Enhancements of Intel® FMA Data Scrambling Data Swapping LPDDR5/x Ascending and Descending LPDDR4x CMD Mirroring DDR I/O Interleaving DRAM Clock Generation DRAM Reference Voltage Generation Data Swizzling Error Correction With Standard RAM Post Package Repair Refresh Management (RFM)
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
System Memory Timing Support System Memory Timing Support SAGV Points DDR Frequency Shifting
System Memory Timing Support
SAGV Points
DDR Frequency Shifting
Memory Controller (MC)
Memory Controller Power Gate
System Memory Controller Organization Mode (DDR4/5 Only)
System Memory Frequency
Technology Enhancements of Intel® FMA
Data Scrambling
Data Swapping
LPDDR5/x Ascending and Descending
LPDDR4x CMD Mirroring
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair
Refresh Management (RFM)
Integrated Memory Controller (IMC) Power Management
Integrated Memory Controller (IMC) Power Management Disabling Unused System Memory Outputs DRAM Power Management and Initialization DDR Electrical Power Gating Power Training
Disabling Unused System Memory Outputs
DRAM Power Management and Initialization
DRAM Power Management and Initialization Initialization Role of CKE Conditional Self-Refresh Dynamic Power-Down DRAM I/O Power Management
Initialization Role of CKE
Conditional Self-Refresh
Dynamic Power-Down
DRAM I/O Power Management
DDR Electrical Power Gating
Power Training
USB-C* Sub System
USB-C* Sub System General Capabilities USB* 4 Router USB-C Sub-system xHCI/xDCI Controllers USB-C Sub-System Display Interface
General Capabilities
USB* 4 Router
USB* 4 Router USB 4 Host Router Implementation Capabilities
USB 4 Host Router Implementation Capabilities
USB-C Sub-system xHCI/xDCI Controllers
USB-C Sub-system xHCI/xDCI Controllers USB 3 Controllers USB-C Sub-System PCIe Interface
USB 3 Controllers
USB-C Sub-System PCIe Interface
USB-C Sub-System Display Interface
PCIe* Interface
PCIe* Interface Processor PCI Express* Interface
Processor PCI Express* Interface
Processor PCI Express* Interface PCI Express* Support PCI Express* Architecture PCI Express* Configuration Mechanism PCI Express* Equalization Methodology PCI Express* Hot Plug
PCI Express* Support
PCI Express* Architecture
PCI Express* Configuration Mechanism
PCI Express* Equalization Methodology
PCI Express* Hot Plug
Direct Media Interface and On Package Interface
Direct Media Interface (DMI) On Package Interface (OPI)
Direct Media Interface (DMI)
Direct Media Interface (DMI) DMI Error Flow DMI Link Down
DMI Error Flow
DMI Link Down
On Package Interface (OPI)
OPI Support Functional Description
OPI Support
Functional Description
Graphics
Graphics Processor Graphics
Processor Graphics
Processor Graphics Media Support (Intel® QuickSync and Clear Video Technology HD) Platform Graphics Hardware Feature
Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD) Hardware Accelerated Video Decode Hardware Accelerated Video Encode Hardware Accelerated Video Processing Hardware Accelerated Transcoding
Hardware Accelerated Video Decode
Hardware Accelerated Video Encode
Hardware Accelerated Video Processing
Hardware Accelerated Transcoding
Platform Graphics Hardware Feature
Platform Graphics Hardware Feature Hybrid Graphics
Hybrid Graphics
Display
Display Display Technologies Support Display Configuration Display Features
Display Technologies Support
Display Configuration
Display Features
Display Features General Capabilities Multiple Display Configurations High-bandwidth Digital Content Protection (HDCP) DisplayPort* High-Definition Multimedia Interface (HDMI*) embedded DisplayPort* (eDP*) MIPI* DSI Integrated Audio
General Capabilities
Multiple Display Configurations
High-bandwidth Digital Content Protection (HDCP)
DisplayPort*
DisplayPort* Multi-Stream Transport (MST)
Multi-Stream Transport (MST)
High-Definition Multimedia Interface (HDMI*)
embedded DisplayPort* (eDP*)
MIPI* DSI
Integrated Audio
Camera/MIPI
Camera/MIPI Camera Pipe Support MIPI* CSI-2 Camera Interconnect
Camera Pipe Support
MIPI* CSI-2 Camera Interconnect
MIPI* CSI-2 Camera Interconnect Camera Control Logic Camera Modules CSI-2 Lane Configurations
Camera Control Logic
Camera Modules
CSI-2 Lane Configurations
Signal Description
Signal Description System Memory Interface PCI Express* Graphics (PEG) Signals Direct Media Interface (DMI) Signals Reset and Miscellaneous Signals Display Interfaces USB Type-C Signals MIPI CSI 2 Interface Signals Processor Clocking Signals Testability Signals Error and Thermal Protection Signals Processor Power Rails Ground and Reserved Signals Processor Internal Pull-Up / Pull- Down on Package
System Memory Interface
System Memory Interface DDR4 Memory Interface LP4x-LP5 Memory Interface DDR5 Memory Interface
DDR4 Memory Interface
LP4x-LP5 Memory Interface
DDR5 Memory Interface
PCI Express* Graphics (PEG) Signals
Direct Media Interface (DMI) Signals
Reset and Miscellaneous Signals
Display Interfaces
Display Interfaces Digital Display Interface (DDI) Signals Digital Display Audio Signals
Digital Display Interface (DDI) Signals
Digital Display Audio Signals
USB Type-C Signals
MIPI CSI 2 Interface Signals
Processor Clocking Signals
Testability Signals
Error and Thermal Protection Signals
Processor Power Rails
Ground and Reserved Signals
Processor Internal Pull-Up / Pull- Down on Package
Electrical Specifications
Electrical Specifications Processor Power Rails DC Specifications
Processor Power Rails
Processor Power Rails Power and Ground Pins Voltage Regulator VCC Voltage Identification (VID)
Power and Ground Pins
Voltage Regulator
VCC Voltage Identification (VID)
DC Specifications
DC Specifications Processor Power Rails DC Specifications Processor Interfaces DC Specifications
Processor Power Rails DC Specifications
Processor Power Rails DC Specifications VCCCORE DC Specifications VccGT DC Specifications VDD2 DC Specifications Vcc1P05_PROC DC Specifications Vcc1P8_PROC DC Specifications
VCCCORE DC Specifications
VccGT DC Specifications
VDD2 DC Specifications
Vcc1P05_PROC DC Specifications
Vcc1P8_PROC DC Specifications
Processor Interfaces DC Specifications
Processor Interfaces DC Specifications DDR4 DC Specifications DDR5 DC Specifications LPDDR4x DC Specification LPDDR5/x DC Specification PCIe* DC and Timing Specifications PCI Express* Graphics (PEG) Group DC Specifications Digital Display Interface (DDI) DC Specifications CMOS DC Specifications GTL and OD DC Specification PECI DC Characteristics
DDR4 DC Specifications
DDR5 DC Specifications
LPDDR4x DC Specification
LPDDR5/x DC Specification
PCIe* DC and Timing Specifications
PCI Express* Graphics (PEG) Group DC Specifications
Digital Display Interface (DDI) DC Specifications
CMOS DC Specifications
GTL and OD DC Specification
PECI DC Characteristics
Package Mechanical Specifications
Package Mechanical Specifications Package Mechanical Attributes Package Storage Specifications
Package Mechanical Attributes
Package Storage Specifications
CPU And Device IDs
CPU And Device IDs CPUID PCI Configuration Header Device IDs
CPUID
PCI Configuration Header
Device IDs
Legal Disclaimer
Revision History
Introduction
Technologies
Power Management
Thermal Management
Memory
USB-C* Sub System
PCIe* Interface
Direct Media Interface and On Package Interface
Graphics
Display
Camera/MIPI
Signal Description
Electrical Specifications
Package Mechanical Specifications
CPU And Device IDs

PCI Express* Support

The S processor PCI Express* has two interfaces:

  • 16-lane (x16) port supporting PCIE to gen 5.0 or below that can also be configured as multiple ports at narrower widths.
  • 4-lane (x4) port supporting PCIE gen 4.0 or below.

The HX processor line PCI Express* has two interfaces:

  • 16-lane (x16) port supporting PCIE to gen 5.0 or below that can also be configured as multiple ports at narrower widths.
  • 4-lane (x4) port supporting PCIE gen 4.0 or below.

The H45 processor line PCI Express* has three interfaces:

  • One 8-lane (x8) port supporting PCIE to gen 5.0 or below. This interface is available on certain SKU
  • Two 4-lane (x4) port supporting PCIE gen 4.0 or below.

The PX processor line PCI Express* has two interfaces:

  • One 8-lane (x8) port supporting PCIE to gen 4.0 or below. This interface is available on certain SKU
  • One 4-lane (x4) port supporting PCIE gen 4.0 or below.

The P processor line PCI Express* has two interfaces:

  • Two 4-lane (x4) port supporting PCIE gen 4.0 or below.

The U processor line PCI Express* has two interfaces:

  • Two 4-lane (x4) port supporting PCIE gen 4.0 or below.

The processor supports the following:

PCIe Controller Feature S/HX - Processor Line H/PX - Processor Line P/U - Processor Line
PEG10 PEG11 PEG60 PEG10 PEG60 PEG62 PEG60 PEG62
PCIe Gen

Gen5

Gen5

Gen4

Gen5 (H)

Gen4 (PX)

Gen4 Gen4 Gen4 Gen4
dGPU support Yes Yes No Yes Yes Yes Yes [P],

Yes [U]6

Yes [P],

Yes [U]6

SSD support Yes Yes Yes Yes Yes Yes Yes Yes
Dynamic Width Change Support Yes Yes Yes Yes Yes Yes Yes Yes
Dynamic Speed Change Support No No No No No No No No
L1 PM Sub-States (L1.0, L1.1, L1.2) Yes Yes Yes Yes Yes Yes Yes Yes
L0s Link State (RX/TX) Yes Yes No Yes Yes Yes Yes Yes
S3/S4/S5 Sleep States (Sx) Yes Yes Yes Yes Yes Yes Yes Yes
Hierarchical configuration mechanism Yes Yes Yes Yes Yes Yes Yes Yes
Traditional PCI style traffic (asynchronous snooped, PCI ordering) Yes Yes Yes Yes Yes Yes Yes Yes
Extended configuration space Yes Yes Yes Yes Yes Yes Yes Yes
Enhanced Access Mechanism4 Yes Yes Yes Yes Yes Yes Yes Yes
64-bit downstream address format2 Yes Yes Yes Yes Yes Yes Yes Yes
64-bit upstream address format3 Yes Yes Yes Yes Yes Yes Yes Yes
Common Clock Mode Yes Yes Yes Yes Yes Yes Yes Yes
Separate Reference Clock with Independent SSC (SRIS)4 No No No No No No No No
Separate Reference Clock with No SSC (SRNS) No No No No No No No No
Precision Time Measurement (PTM) Yes Yes Yes1 Yes Yes1 Yes1 Yes1 Yes1
Advanced Error Reporting (AER) Yes Yes Yes Yes Yes Yes Yes Yes
End-to-End Lane Reversal Yes Yes Yes Yes Yes Yes Yes Yes
Latency Tolerance Reporting (LTR) Yes Yes Yes Yes Yes Yes Yes Yes
PCIe TX Half Swing No No No No No No No No
PCIe TX Full Swing Yes Yes Yes Yes Yes Yes Yes Yes
Run Time D3 (RTD3) Yes Yes Yes Yes Yes Yes Yes Yes
Modern Standby Yes Yes Yes Yes Yes Yes Yes Yes
MCTP VDM tunneling Yes Yes Yes Yes Yes Yes Yes Yes
Message Signaled Interrupt (MSI) messages5 Yes Yes Yes Yes Yes Yes Yes Yes
Access Control Services (ACS) Yes Yes Yes Yes Yes Yes Yes Yes
Alternative Routing-ID Interpretation (ARI) Yes Yes Yes Yes Yes Yes Yes Yes
Port 80h Decode Yes Yes Yes Yes Yes Yes Yes Yes
Receive Lane Polarity Inversion Yes Yes Yes Yes Yes Yes Yes Yes
PCIe Controller Root Port Hot-Plug No No No No No No No No
Downstream Port Containment (DPC) Yes Yes Yes Yes Yes Yes Yes Yes
Enhanced Downstream Port Containment (eDPC) No No No No No No No No
Virtual Channel (VC) VC0 VC0 VC0/VC1 VC0 VC0/VC1 VC0/VC1 VC0/VC1 VC0/VC1
NVMe Cycle Router No No No No No No No No
Volume Management Device (Intel® VMD) Support Yes Yes Yes Yes Yes Yes Yes Yes
Discrete Device Support (M.2 1px2, 1px4) Yes Yes Yes Yes Yes Yes Yes Yes
Hybrid Dual Port Module Support (M.2 2px2) No No No No No No No No
Peer-2-Peer (P2P) Mem Write Transactions No No Yes No No Yes Yes Yes
Peer-2-Peer (P2P) Mem Read Transactions No No No No No No No No
Peer-2-Peer (P2P) MCTP Transactions Yes Yes Yes Yes Yes Yes Yes Yes

  1. Byte order ECN not supported

  2. 4096 GB limit (Bits 63:43 always zeros)
  3. Processor responds to upstream read transactions to addresses above 4096 GB (addresses where any of Bits 63:43 are non-zero) with an Unsupported Request response. Upstream write transactions to addresses above 4096 GB will be dropped
  4. SRIS is enabled in PCH PCIe RP and not in CPU PCIe RP
  5. Only MSI is supported, MSI-X is not supported (no need for many vector)
  6. U dGPU is supported but not validated
  • Hierarchical PCI-compliant configuration mechanism for downstream devices.
  • Traditional PCI style traffic (asynchronous snooped, PCI ordering).
  • PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space.
  • PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory-mapped fashion.
  • Automatic discovery, negotiation, and training of link out of reset.
  • Multiple Virtual Channel for Gen 4 port only*.
  • 64-bit downstream address format, but the processor never generates an address above 4096 GB (Bits 63:43 will always be zeros).
  • 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 4096 GB (addresses where any of Bits 63:43 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 4096 GB will be dropped.
  • Re-issues Configuration cycles that have been previously completed with the Configuration Retry status.
  • PCI Express* reference clock is a 100-MHz differential clock.
  • Power Management Event (PME) functions.
  • Modern standby
  • Dynamic width capability.
  • Message Signaled Interrupt (MSI and MSI-X) messages.
  • Lane reversal
  • Advanced Error Reporting (AER)
  • MCTP VDM tunneling.
  • ACS - Access control services
  • Hotplug is supported on PEG60/62 only. It is not supported on PEG10/11
  • Precision Time Measurement (PTM) - This feature is supported on PEG60/62 with the exception of ECN for byte ordering of the PTM value not being supported. PEG10/11 do support ECN for byte ordering

The S/HX processor supports the configurations shown in the following tables:

PCI Express* 16 - Lane Bifurcation and Lane Reversal Mapping

Bifurcation Link Width CFG Signals Lanes
0:1:0 0:1:1

CFG

[6]

CFG

[5]

CFG

[2]

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PCIe controller PCIe 010 (PEG10)
1x16 x16 N/A 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1x16

Reversed

x16 N/A 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIe controller PCIe 010 (PEG10) PCIe 011 (PEG11)
2x8 x8 x8 1 0 1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
PCIe controller PCIe 011 (PEG11) PCIe 010 (PEG10)
2x8

Reversed

x8 x8 1 0 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Notes:
  1. For CFG bus details, refer to Reset and Miscellaneous Signals.
  2. Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported.
  3. In case that more than one device is connected, the device with the highest lane count, should always be connected to the lower lanes, as follows:
    1. Connect lane 0 of 1st device to lane 0.
    2. Connect lane 0 of 2nd device to lane 8.
  4. For reversal lanes, for example: When using 1x8, the 8 lane device should use lanes 8:15, so lane 15 will be connected to lane 0 of the Device.

S/HX - Processor PCI Express* 4 - Lane Reversal Mapping

Bifurcation

Link Width

CFG Signals

Lanes

0:6:0

CFG [14]

0

1

2

3

PCIe controller PCIe 060 (PEG60)

1x4

x4

1

0

1

2

3

1x4 Reversed

x4

0

3

2

1

0

Note:PCIe* Port60 is a single x4 port without bifurcation capabilities, thus bifurcation pin straps are not applicable.

The H/PX processor Lines supports the configurations shown in the following tables:

H/PX PCI Express* 8 - Lane Reversal Mapping

Bifurcation Link Width CFG Signals Lanes
0:1:0 0:1:1

CFG

[6]

CFG

[5]

CFG

[2]

0 1 2 3 4 5 6 7
PCIe controller PCIe 010 (PEG10)
1x8 x8 N/A 1 1 1 0 1 2 3 4 5 6 7
1x8

Reversed

x8 N/A 1 1 0 7 6 5 4 3 2 1 0
Notes:
  1. For CFG bus details, refer to Reset and Miscellaneous Signals.
  2. Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported.
  3. For reversal lanes, for example: When using 1x4, the 4 lane device should use lanes 4:7, so lane 7 will be connected to lane 0 of the Device.

The H/PX/P/U processor Lines supports the configurations shown in the following tables:

H/PX/P/U PCI Express* 4 - Lane Reversal Mapping

Bifurcation

Link Width

CFG Signals

Lanes

0:6:0

0:6:2

CFG [14]

CFG [15]

0

1

2

3

PCIe Controller PCIe 060 (PEG60)

1x4

x4

NA

1

NA

0

1

2

3

1x4 Reversed

x4

NA

0

NA

3

2

1

0

PCIe Controller PCIe 062 (PEG62)

1x4

NA

x4

NA

1

0

1

2

3

1x4 Reversed

NA

x4

NA

0

3

2

1

0

PCI Express* Maximum Transfer Rates and Theoretical Bandwidth

PCI Express* Generation

Encoding

Maximum Transfer Rate

[GT/s]

Theoretical Bandwidth [GB/s]

S/H/HX/P/U

x4

S/H/HX

x8

S/HX

x16

Gen 1

8b/10b

2.5

1.0

2.0

4.0

Gen 2

8b/10b

5

2.0

4.0

8.0

Gen 3

128b/130b

8

3.9

7.9

15.8

Gen 4

128b/130b

16

7.9

15.8

31.5

Gen 5

128b/130b

321

15.81

31.51

631

Note:1. Transfer rate and max theoretical Bandwidth are not final and could be lowered.

The above table summarizes the transfer rates and theoretical bandwidth of PCI Express* link.

PCI Express* Architecture