Identification Information

11th Generation Intel® Core™ Processor

Specification Update

ID	Date	Version	Classification
631123	03/01/2026		Intel Confidential

Component Identification via Programming Interface

The processor stepping is identified by the following register contents:

Table 2-1. Processor Lines Component Identification

Processor	CPUID	Reserved [31:28]	Extended Family [27:20]	Extended Model [19:16]	Reserved [15:14]	Processor Type [13:12]	Family Code [11:8]	Model Number [7:4]	Stepping ID [3:0]
UP3/UP4/H35	000806C1h	Reserved	0000000b	1000b	Reserved	00b	0110b	1100b	0001b
H81	000806D1h	Reserved	0000000b	1000b	Reserved	00b	0110b	1101b	0001b
UP3-Refresh/ H35-Refresh	000806C2h	Reserved	0000000b	1000b	Reserved	00b	0110b	1100b	0010b

Notes:

The Extended Family, Bits [27:20] are used in conjunction with the Family Code, specified in Bits[11:8], to indicate whether the processor belongs to the Celeron^®, Pentium^®, or Intel^® Core™ processor family.
The Extended Model, Bits [19:16] in conjunction with the Model Number, specified in Bits [7:4], are used to identify the model of the processor within the processor’s family.
The Family Code corresponds to Bits [11:8] of the EDX register after RESET, Bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
The Model Number corresponds to Bits [7:4] of the EDX register after RESET, Bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.
The Stepping ID in Bits [3:0] indicates the revision number of that model. Refer table above for the processor stepping ID number in the CPUID information.
When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID value in the EAX register. The EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

Component Marking Information

Figure 2-1. Processor Based on UP3/H35/UP3-Refresh/H35-Refresh Processor Line Multi-Chip Package BGA Top-Side Markings

Pin Count: 1449 Package Size: 45.5 mm x 25 mm

Production (SSPEC):

FPO: FPOxxxxx
{eX}
SWIR1: Intel^® logoNote:“1” is used to extract the unit visual ID (2D ID).
Figure 2-2. Processor Based on UP4 Processor Line Multi-Chip Package BGA Top-Side Markings
Pin Count: 1598 Package Size: 26.5 mm x 18.5 m
Production (SSPEC):
Intel logo BRAND PROC# SPEC SPEED {FPO} {eX}
Note:“1” is used to extract the unit visual ID (2D ID).
Figure 2-3. Processor Based on H81 Processor Line Multi-Chip Package BGA Top-Side Markings
Pin Count: 1787 Package Size (mm): Width x Height: 50 x 26.5
Production (SSPEC):
Intel logo BRAND PROC# SPEC SPEED {FPO} {eX}
Note:“1” is used to extract the unit visual ID (2D ID).
Processor list can be found at: https://ark.intel.com/content/www/us/en/ark/products/codename/88759/products-formerly-tiger-lake.html