11th Generation Intel® Core™ Processor
Specification Update
Summary Tables of Changes
The following tables indicate the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed processor stepping. Intel® intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. These tables use the following notations:
Codes Used in Summary Table
Stepping | Description |
(No mark) or (Blank Box) | This erratum is fixed in listed stepping or specification change does not apply to listed stepping. |
Status | Description |
Doc | Document change or update that is implemented. |
Planned Fix | This erratum may be fixed in a future stepping of the product. |
Fixed | This erratum has been previously fixed in Intel® hardware, firmware, or software. |
No Fix | There are no plans to fix this erratum. |
Errata Summary Table
Erratum ID | Processor Line/Stepping | Title | ||||||
UP3 | IOT UP3 | UP4 | H35 | H81 | UP3-Refresh | H35-Refresh | ||
TGL001 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | X87 FDP Value May be Saved Incorrectly In Real-Address Mode or Virtual-8086 Mode |
TGL002 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL003 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL004 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Placing Posted-Interrupt Descriptors Within the PRMRR May Result In a Processor Hang |
TGL005 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL006 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Intel® PT TIP or FUP Packets May be Dropped Without OVF Packet |
TGL007 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Overflow Flag in IA32_MC0_STATUS MSR May be Incorrectly Set |
TGL008 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL009 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL010 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Processor May Generate Spurious Page Faults On Shadow Stack Pages |
TGL011 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL012 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL013 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Performing an XACQUIRE to an Intel® PT ToPA Table May Lead to Processor Hang |
TGL014 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL015 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL016 | Fixed | Fixed | N/A | N/A | N/A | N/A | N/A | |
TGL017 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Unable to Transmit Modified Compliance Test Pattern At 2.5 GT/S or 5.0 GT/s Link Speeds |
TGL018 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | MSR IA32_THERM_STATUS CURRENT_LIMIT_STATUS May Report Incorrect Value |
TGL019 | Fixed | Fixed | N/A | N/A | N/A | N/A | N/A | |
TGL020 | Fixed | Fixed | N/A | N/A | N/A | N/A | N/A | |
TGL021 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Processor May Hang if Warm Reset Triggers During BIOS Initialization |
TGL022 | Fixed | Fixed | Fixed | Fixed | N/A | N/A | N/A | PCIe* Link_Down May Occur After Exiting From Package C10 Cycle |
TGL023 | No Fix | No Fix | N/A | N/A | N/A | N/A | N/A | |
TGL024 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL025 | Fixed | Fixed | Fixed | N/A | N/A | N/A | N/A | Cache Configuration May be Incorrectly Initialized During Boot |
TGL026 | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A. Erratum has been removed. |
TGL027 | No Fix | No Fix | No Fix | N/A | N/A | N/A | N/A | Processor PCIe* Reference Clock May be Unavailable if CLKREQ# is Asserted During L1.2 Entry |
TGL028 | Fixed | Fixed | Fixed | N/A | N/A | N/A | N/A | |
TGL029 | N/A | N/A | N/A | N/A | No Fix | N/A | N/A | |
TGL030 | Fixed | Fixed | N/A | Fixed | Fixed | Fixed | Fixed | DDR4 1Rx16 DIMMs Cannot Achieve Optimal Memory Configuration |
TGL031 | Fixed | Fixed | Fixed | Fixed | N/A | N/A | N/A | Incorrect Core Operating Voltage May Lead To Unpredictable System Behavior |
TGL032 | Fixed | Fixed | Fixed | Fixed | N/A | N/A | N/A | |
TGL033 | Fixed | Fixed | Fixed | Fixed | N/A | N/A | N/A | |
TGL034 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL035 | Fixed | Fixed | Fixed | Fixed | N/A | N/A | N/A | |
TGL036 | Fixed | Fixed | Fixed | Fixed | N/A | Fixed | Fixed | |
TGL037 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | VCVTPS2PH To Memory May Update MXCSR in The Case of a Fault on the Store |
TGL038 | Fixed | Fixed | Fixed | N/A | N/A | N/A | N/A | |
TGL039 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL040 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL041 | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A. Erratum has been removed. |
TGL042 | N/A | N/A | N/A | N/A | Fixed | N/A | N/A | |
TGL043 | N/A | N/A | N/A | N/A | Fixed | N/A | N/A | Embedded Display Flicker May be Observed During Idle Scenarios |
TGL044 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | False MC1 Error Reported in The Shadow of an Internal Timer Error |
TGL045 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL046 | N/A | N/A | N/A | N/A | Fixed | N/A | N/A | |
TGL047 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL048 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL049 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Intel® Processor Trace PSB+ Packets May Contain Unexpected Packets |
TGL050 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL051 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL052 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Intel® PT Trace May Contain Incorrect Data When Configured With Single Range Output Larger Than 4KB |
TGL053 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | On Instructions Longer Than 15 Bytes, #GP Exception is Prioritized And Delivered Over #CP Exception |
TGL054 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Mismatch on DR6 Value When Breakpoint Match is on Bitmap Address |
TGL055 | Fixed | Fixed | Fixed | Fixed | N/A | N/A | N/A | |
TGL056 | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | USB 3.0 Device May Not be Detected or May Down Train to USB 2.0 Speed |
TGL057 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Call Instruction Wrapping Around The 32-bit Address Boundary May Return to Incorrect Address |
TGL058 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL059 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL060 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL061 | N/A | N/A | N/A | N/A | Fixed | Fixed | Fixed | |
TGL062 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL063 | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | |
TGL064 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Processor May Encrypt TME Exclude Range if Mapped to Remap Range |
TGL065 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL066 | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | |
TGL067 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL068 | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | |
TGL069 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL070 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL071 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | |
TGL072 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Incorrect Last Branch From Value in BTS Branch Record During a Task Switch |
TGL073 | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | No Fix | Certain VMCS Fields May be Incorrect During STM to VMX Transitions |
TGL074 | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | Fixed | MPX_FUSE_OVERRIDE Register May Trigger General Protection Fault |
Specification Changes
No. | Specification Changes |
001 | HDCP 2.2 not supported in certain modes for DP1.4a interface. |
002 | DP-in support of both LTTPR transparent and non-transparent modes. |
Specification Clarifications
No. | Specification Clarifications |
None for this revision of this specification update. |
Documentation Changes
No. | Documentation Changes |
None for this revision of this specification update. |