13th Generation Intel® Core™, Intel® Core™ 14th Generation, Intel® Core™ Processor (Series 1) and (Series 2), Intel® Xeon™ E 2400 Processor and Intel® Xeon™ 6300 Processor
Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S, H, P, HX, and U Processor Line Platforms, formerly known as Raptor Lake.
Supporting Intel® Core™ 14th Generation Processor for S, HX formerly known As Raptor Lake Refresh.
Supporting Intel® Core™ Processor (Series 1) for U Processor Line Platform, formerly known As Raptor Lake refresh
Supporting Intel® Core™ Processor (Series 2) for H Processor Line Platform, formerly known As Raptor Lake Refresh.
Supporting Intel® Xeon® E 2400 Processor and Intel® Xeon® 6300 Processor, formerly known As Raptor Lake–E Refresh
Testability and Monitoring Signals
| Signal Name | Description | Dir. | Buffer Type | Link Type | Availability |
|---|---|---|---|---|---|
| BPM#[3:0] | Breakpoint and Performance Monitor Signals: Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. | I/O | GTL | SE | S H/P Processor Line U |
| PROC_PRDY# | Probe Mode Ready: PROC_PRDY# is a processor output used by debug tools to determine processor debug readiness. | O | OD | SE | S H/P Processor Line U |
| PROC_PREQ# | Probe Mode Request: PROC_PREQ# is used by debug tools to request debug operation of the processor. | I | GTL | SE | S H/P Processor Line U |
| PROC_TCK | Test Clock: This signal provides the clock input for the processor Test Bus (also known as the Test Access Port). This signal should be driven low or allowed to float during power on Reset. | I | GTL | SE | S |
| PROC_TDI | Test Data In: This signal transfers serial test data into the processor. This signal provides the serial input needed for JTAG specification support. | I | GTL | SE | S |
| PROC_TDO | Test Data Out: This signal transfers serial test data out of the processor. This signal provides the serial output needed for JTAG specification support. | O | OD | SE | S |
| PROC_TMS | Test Mode Select: A JTAG specification support signal used by debug tools. | I | GTL | SE | S |
| PROC_JTAG_TCK | Test Clock: This signal provides the clock input for the processor Test Bus (also known as the Test Access Port). This signal should be driven low or allowed to float during power on Reset. | I | GTL | SE | H/P/U/U Refresh Processor Line |
| PROC_JTAG_TDI | Test Data In: This signal transfers serial test data into the processor. This signal provides the serial input needed for JTAG specification support. | I | GTL | SE | H/P/U/U Refresh Processor Line |
| PROC_JTAG_TDO | Test Data Out: This signal transfers serial test data out of the processor. This signal provides the serial output needed for JTAG specification support. | O | OD | SE | H/P/U/U Refresh Processor Line |
| PROC_JTAG_TMS | Test Mode Select: A JTAG specification support signal used by debug tools. | I | GTL | SE | H/P/U/U Refresh Processor Line |
| PROC_JTAG_TRST# | Test Reset: Resets the Test Access Port (TAP) logic. This signal should be driven low during power on Reset. Refer to the appropriate processor Debug Port Design Guide for complete implementation details. | I | GTL | SE | S H/P/U/U Refresh Processor Line |
| DBG_PMODE | Processor debug mode | O | GTL | SE | H/P/U/U Refresh Processor Line |