Intel® Core™ Ultra 200S, Intel® Core™ Ultra 200S Plus ,Intel® Core™ Ultra 200HX and 200HX Plus Series Processors
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 832586 | 03/17/2026 | Public |
Legal Disclaimer
Revision History
Introduction
Processor and Device IDs
Package Mechanical Specifications
Memory Mapping
Security Technologies
Intel® Virtualization Technology (Intel® VT)
Instructions Set Enhancements
Platform Environmental Control Interface (PECI)
Intel GMM and Neural Network Accelerator (Intel GNA 3.5)
Intel® Neural Processing Unit (Intel® NPU)
Power Management
Power Delivery
Electrical Specifications
Thermal Management
Clock Topology
Memory
USB Type-C* Sub System
Intel® Volume Management Device (Intel® VMD) Technology
PCI Express* (PCIe*)
Graphics
Display
General Purpose Input and Output
Interrupt Timer Subsystem (ITSS)
Direct Media Interface (DMI)
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Testability and Monitoring
Miscellaneous Signals
Security Technologies
Intel® Converged Boot Guard and Intel® TXT
Crypto Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Prevention (Intel® SMEP)
Intel® Supervisor Mode Access Prevention (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
KeyLocker Technology
Intel® System Resources Defense and Intel® System Security Report
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Security Firmware Engines
Power and Performance Technologies
Intel® Thread Director
Intel® Smart Cache Technology
P-core and E-core Level 0, Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Technology 2.0
Intel® Turbo Boost Max Technology 3.0
Intel® Adaptive Boost Technology
Intel® System Agent Enhanced SpeedStep ® Technology
Enhanced Intel SpeedStep® Technology
Intel® Thermal Velocity Boost (Intel® TVB)
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (Intel® DTT)
Cache Line Write Back (CLWB)
User Mode Wait Instructions
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THERMTRIP# Signal
Critical Temperature Detection
Software Controlled Clock Modulation (On-Demand Mode)
System Memory Interface
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
Memory Controller (MC)
System Memory Controller Organization Mode
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
ECC H-Matrix Syndrome Codes
Data Swapping
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Post Package Repair (PPR)
Intel® APIC Virtualization Technology (Intel® APICv)
APIC virtualization is a collection of features that can be used to support the virtualization of interrupts and the Advanced Programmable Interrupt Controller (APIC).
When APIC virtualization is enabled, the processor emulates many accesses to the APIC, tracks the state of the virtual APIC, and delivers virtual interrupts — all in VMX non-root operation without a VM exit.
The following are the VM-execution controls relevant to APIC virtualization and virtual interrupts:
- Virtual-interrupt Delivery: This controls enables the evaluation and delivery of pending virtual interrupts. It also enables the emulation of writes (memory-mapped or MSR-based, as enabled) to the APIC registers that control interrupt prioritization.
- Use TPR Shadow: This control enables emulation of accesses to the APIC’s task-priority register (TPR) via CR8 and, if enabled, via the memory-mapped or MSR-based interfaces.
- Virtualize APIC Accesses: This control enables virtualization of memory-mapped accesses to the APIC by causing VM exits on accesses to a VMM-specified APIC-access page. Some of the other controls, if set, may cause some of these accesses to be emulated rather than causing VM exits.
- Virtualize x2APIC Mode: This control enables virtualization of MSR-based accesses to the APIC.
- APIC-register Virtualization: This control allows memory-mapped and MSR-based reads of most APIC registers (as enabled) by satisfying them from the virtual-APIC page. It directs memory-mapped writes to the APIC-access page to the virtual-APIC page, following them by VM exits for VMM emulation.
- Process Posted Interrupts: This control allows software to post virtual interrupts in a data structure and send a notification to another logical processor; upon receipt of the notification, the target processor will process the posted interrupts by copying them into the virtual-APIC page.
Intel® APIC Virtualization specifications and functional descriptions are included in the Intel® 64 Architectures Software Developer’s Manual, Volume 3. Available at: