Memory Map

Legal Disclaimer
Revision History
Introduction
Processor and Device IDs
Package Mechanical Specifications
- Package Mechanical Attributes
- Package Storage Specifications
Memory Mapping
- Functional Description
- Memory Map
  - Boot Block Update Scheme
Security Technologies
Intel® Virtualization Technology (Intel® VT)
Instructions Set Enhancements
- CMPccXADD
- LAM
Platform Environmental Control Interface (PECI)
- PECI Bus Architecture
Intel GMM and Neural Network Accelerator (Intel GNA 3.5)
Intel® Neural Processing Unit (Intel® NPU)
- Functional Description
  - Processor Subsystem
  - NCE Subsystem
Power Management
Power Delivery
Electrical Specifications
- Processor Power Rails
  - Power and Ground Pins
  - VCC Voltage Identification (VID)
- DC Specifications
  - Processor Power Rails DC Specifications
  - Processor Interfaces DC Specifications
Thermal Management
Clock Topology
- Integrated Reference Clock PLL
- Processor Clocking Signals
Memory
USB Type-C* Sub System
Intel® Volume Management Device (Intel® VMD) Technology
PCI Express* (PCIe*)
Graphics
- Processor Graphics
  - Media Support (Intel® QuickSync and Clear Video Technology HD)
  - Graphics Core Cache
- Platform Graphics Hardware Feature
  - Hybrid Graphics
Display
General Purpose Input and Output
- Functional Description
- Signal Description
Interrupt Timer Subsystem (ITSS)
- Feature Overview
- Functional Description
Direct Media Interface (DMI)
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
- Functional Description
- Signal Description
Testability and Monitoring
- Signal Description
- I/O Signal Planes and States
Miscellaneous Signals
- Signal Description
- Ground and Reserved Signals

The following table shows (from the processor perspective) the memory ranges that the processor will decode. Cycles that are not directed to any of the internal memory targets, will be host aborted.

PCIe cycles generated by external PCIe hosts will be positively decoded unless they fall in the PCI-PCI bridge memory forwarding ranges (those addresses are reserved for PCI peer-to-peer traffic). Software must not attempt locks to the processor’s memory-mapped I/O ranges.

Note:Total ports are different for the different SKUs.

Processor Memory Decode Ranges (Processor Perspective)

Memory Range	Target	Dependency/Comments
FECX X000 - FECX X040	I/O(x)APIC inside SOC-S, or behind SOC-S's PCIe root-port	XX controlled via APIC Range Select (ASEL) field and APIC Enable (AEN) bit. For PCIe root port, I/OxApic Enable (PAE) bit
FFFC 0000 - FFFF FFFF	Intel^® CSME	Always enabled. Refer to Section 6.3 on the Top-Block Swap
FED0 X000 - FED0 X3FF	HPET	BIOS determines "fixed" location which is one of four 1KB ranges where X (in the first column) is 0h, 1h, 2h, or 3h.
FED4 8000 - FED4 BFFF	LPC	Always enabled - LT address range NOTE: the LPC "bus" interface is removed, but the LPC HW is retained to support this register set.
FED4 C000 - FED4 FFFF	Internal (PSF Error Handler)	Always enabled
FED5 0000 - FED5 FFFF	ESE++	Always enabled
FED6 0000 - FED6 1FFF	xHCI	NOT positively decoded in PCH(DMI/PSF)
FED6 2000 - FED6 3FFF	xHCI (CPU )	Fixed range in CPU - never forwarded to PCH. First implemented in ICL
FED7 0000 - FED7 4FFF	Internal Device	Security feature related
DMI General Purpose Memory ranges (1 to 3)	General purpose	Enable via setting the Decode Enable bit of the respective Memory Range register
MMIO resources for VMD managed devices	Storage devices	Enable through the VMD device in SOC

Boot Block Update Scheme

Variable I/O Decode Ranges Boot Block Update Scheme