Peripheral Channel

PCH eSPI Attached External EC/Device IO/Memory Cycles

The processor routes the eSPI peripheral channel fixed IO, generic IO/memory cycles to the processor Direct eSPI controller through the peripheral channel to the PCH Direct eSPI target. Then the BIOS sends these IO/memory cycles to different external eSPI devices attached to the PCH. The PCH eSPI switch will route them to different eSPI devices based on the IOE/IOD/LGMR register setting on the PCH eSPI controller.

The PCH eSPI switch forwards the EC bus mastering memory cycles and LTR messages between the processor Direct eSPI controller and an EC attached to the PCH.

PCH RTC Port

The processor Direct eSPI controller access and sends the IO cycle to the RTC IO port through the PCH on the peripheral channel and the completion is converted back to the processor.

PCH IP Register Access

The PCH IP register space for SPI/eSPI, GPIO, RTC, and IOxAPIC can be accessed by the processor BIOS using the reserved window of the processor Direct eSPI controller peripheral channel device 0 Generic memory range(LGMR). The BIOS access can be locked using a lock bit in the PCH eSPI private register.

Virtual Wire Channel

The processor PMC, ITSS, and GPIO transmit/receive virtual wires to/from the PCH attached EC. The VWs are forwarded to/from the EC by the PCH eSPI switch.

The GPIO VWs are also supported between the processor GPIO controller and the PCH attached EC in both directions.

A new upstream VW is added to support PCH NMI reporting. The processor Direct eSPI controller forwards this VW to the processor ITSS.

The processor Direct eSPI controller does not broadcast the power management VWs (e.g. PLTSRT/SLP_​Sx etc) using the PCH DIrect eSPI target. The PCH takes responsibility to broadcast the power management VWs if there are multiple eSPI devices attached to the PCH.

OOB Channel

The processor PMC, Intel^® CSME, Intel^® Silicon Security Engine, TCSS, DFx tracing, and the RTC uses the Direct eSPI to communicate to the PCH via the OOB channel. The processor PMC also uses the legacy OOB interface with PCH attached EC for other OOB services including PECI over eSPI.

Flash Channel

The processor BIOS, CSME, and ESE use the processor SPI controller for flash access in SAF mode. The BIOS also uses the processor SPI controller for RPMC access in SAF mode. The PCH CSME uses PCH SPI controller for RPMC access.

To improve the flash access/boot time in the desktop platform, the processor BIOS initializes the DMA. During the DMA flow, it sends multiple read requests for the processor and the PCH to the flash device to optimize the performance.

The processor descriptor contains the region definitions and descriptor based permission control. The processor SPI controller accesses its descriptor on PCH Flash or EC via the SAF channel between the processor and the PCH.

The PCH CSME share region 2 and the processor ESE and the PCH ESE share region 10. The other region assignment is listed in the table below.

Processor BIOS FRACC (Flash Region Access Permission) Control

The BIOS FRACC and SFRACC (Secondary FRACC) grant permission to ESE (in Processor and the PCH) to read/write access to the BIOS/secondary BIOS region in the flash. To provide BIOS to access the PCH SPI controller's control registers FRACC and SFRACC, the PCH SPI controller's BIOS PCI configuration and MMIO registers are mapped to the processor's Direct eSPI peripheral channel generic memory range.

The processor and the PCH expose the PCH SPI controller to BIOS through DMI so that BIOS can directly program the BIOS FRACC from the PCH SPI controller to grant access to the BIOS in the PCH flash.

Processor BIOS Software Sequencing

The processor only supports SAF mode on the Direct eSPI. The BIOS software sequencing is not supported in SAF mode. To use this feature on the platform, the processor and the PCH exposes the PCH SPI controller to BIOS through DMI so that BIOS can directly program the software sequencing from PCH SPI controller to send software sequencing cycles.