Intel® Core™ Ultra Processor
Datasheet, Volume 1 of 2
Supporting Intel® Core™ Ultra Processor for U/H/U-Type4-series Platforms, formerly known as Meteor Lake
| ID | Date | Version | Classification |
|---|---|---|---|
| 792044 | 03/05/2024 | Public |
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Power Management
Device Power Down Support
In order to power down peripherals connected to
Latency Tolerance Reporting (LTR)
Latency Tolerance Reporting is used to allow the system to optimize internal power states based on dynamic data, comprehending the current platform activity and service latency requirements. The UART bus architecture, however, does not provide the architectural means to define dynamic latency tolerance messaging. Therefore, the interface supports this by reporting its service latency requirements to the platform power management controller via LTR registers.
The controller’s latency tolerance reporting can be managed by one of the two following schemes. The platform integrator must choose the correct scheme for managing latency tolerance reporting based on the platform, OS and usage.
- Platform/HW Default Control. This scheme is used for usage models in which the controller’s state correctly informs the platform of the current latency requirements. In this scheme, the latency requirement is a function of the controller state. The latency for transmitting data to/from its connected device at a given rate while the controller is active is representative of the active latency requirements. On the other hand if the device is not transmitting or receiving data and idle, there is no expectation for end to end latency.
- Driver Control. This scheme is used for usage models in which the controller state does not inform the platform correctly of the current latency requirements. If the FIFOs of the connected device are much smaller than the controller FIFOs, or the connected device’s end to end traffic assumptions are much smaller than the latency to restore the platform from low power state, driver control should be used.