Intel® Core™ Ultra Processor
Datasheet, Volume 1 of 2
Supporting Intel® Core™ Ultra Processor for U/H/U-Type4-series Platforms, formerly known as Meteor Lake
| ID | Date | Version | Classification |
|---|---|---|---|
| 792044 | 03/05/2024 | Public |
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Revision History
Introduction
Processor and Device IDs
Package Mechanical Specifications
Memory Mapping
Security Technologies
Intel® Virtualization Technology (Intel® VT)
Platform Environmental Control Interface (PECI)
Intel® Image Processing Unit (Intel® IPU6)
Intel® Neural Processing Unit (Intel® NPU)
Audio Voice and Speech
Power Management
Power Delivery
Electrical Specifications
Thermal Management
System Clocks
Real Time Clock (RTC)
Memory
USB Type-C* Sub System
Universal Serial Bus (USB)
PCI Express* (PCIe*)
Serial ATA (SATA)
Intel® Volume Management Device (Intel® VMD) Technology
Graphics
Display
Processor Sideband Signals
General Purpose Input and Output
Interrupt Timer Subsystem (ITSS)
GPIO Serial Expander
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Gigabit Ethernet Controller
Connectivity Integrated (CNVi)
Controller Link
Integrated Sensor Hub (ISH)
System Management
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Private Configuration Space Port ID
Testability and Monitoring
Miscellaneous Signals
Security Technologies
Intel® Converged Boot Guard and Intel® TXT
Crypto Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Prevention (Intel® SMEP)
Intel® Supervisor Mode Access Prevention (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
KeyLocker Technology
Intel® Hardware Shield
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Security Firmware Engines
Intel® Virtualization Technology (Intel® VT)
Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Architecture (Intel® VT-x)
Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)
Intel® APIC Virtualization Technology (Intel® APICv)
Hypervisor-Managed Linear Address Translation (HLAT)
Audio Voice and Speech
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S / PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Power Management
System Power States, Advanced Configuration and Power Interface (ACPI)
Legacy Power Management Support
Functional Description
Processor IA Core Power Management
Processor Graphics Power Management
TCSS Power State
Power and Performance Technologies
Deprecated Technology
Power and Internal Signals
Power and Performance Technologies
Intel® Smart Cache Technology
P-core, E-core, and LP E-core Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Max Technology 3.0
Intel® Hyper-Threading Technology (Intel® HT Technology)
Intel® Turbo Boost Technology 2.0
System Agent Enhanced Intel SpeedStep® Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® 64 Architecture x2APIC
Intel® Transactional Synchronization Extensions (Intel ®TSX-NI)
Intel® Dynamic Tuning Technology (Intel® DTT)
Intel® GMM and Neural Network Accelerator (Intel® GNA 3.0)
Cache Line Write Back (CLWB)
Remote Action Request (RAR)
User Mode Wait Instructions
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THERMTRIP# Signal
Critical Temperature Detection
Software Controlled Clock Modulation (On-Demand Mode)
System Memory Interface
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
Memory Controller (MC)
System Memory Controller Organization Mode
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
LPDDR5/x CMD/ADD Ascending and Descending
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
Signal Description
| Signal Name | Type | Description |
|---|---|---|
| Processor JTAG Signals | ||
| PROC_JTAG_TCK | I | Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic. |
| PROC_JTAG_TMS | I | Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations. |
| PROC_JTAG_TDI | I | Test Data Input (TDI): Serial test instructions and data is received by the test logic at TDI. |
| PROC_JTAG_TDO | O | Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard. |
| PROC_JTAG_TRST# | I | Test Reset(TRST): Resets the Test Access Port (TAP) logic. This signal should be driven low during power-on Reset. |
| DBG_PMODE | O | ITP Power Mode Indicator. This signal is used to transmit processor and power/reset information to the Debugger. |
| PRDY# | O | Probe Mode Ready: PRDY# is a processor output used by debug tools to determine processor debug readiness. |
| PREQ# | I | Probe Mode Request: PREQ# is used by debug tools to request debug operation of the processor. |
| Boundary Scan Sideband Signals | ||
| | I/O | BSSB_LS_TX: Boundary Scan Sideband Low Speed Transmit for debug purposes |
| | I/O | BSSB_LS_RX: Boundary Scan Sideband Low Speed Receive for debug purposes |
| Breakpoint and Performance Monitor Signals | ||
| BPM[0] | I/O | Breakpoint and Performance Monitor Signals(BPM): Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. |
| BPM[1] | I/O | Breakpoint and Performance Monitor Signals(BPM): Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. |
| BPM[2] | I/O | Breakpoint and Performance Monitor Signals(BPM): Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. |
| BPM[3] | I/O | Breakpoint and Performance Monitor Signals(BPM): Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. |
| Boot Halt Signal | ||
| I/O | Boot Halt : This signal is used for platform boot halt. Supports 1.8 V only. | |