ATX Version 3 Multi Rail Desktop Platform Power Supply

Design Guide

ID 336521
Date 11/01/2023
Document Table of Contents

CARD_CBL_PRES# (Optional in Power Supply)

This sideband signal has two functions:

  • Primary Function:
    • In its primary role, this sideband conductor provides a constant DC logic signal from the Add-in Card to the power supply to indicate that the 12V-2x6 Auxiliary Power Connector is correctly attached to an Add-in Card.
    • While the power supply is not required to support this signal, every PCIe* CEM Add-in Card mounting the 12V-2x6 PCB Header connector must support this primary function of CARD_​CBL_​PRES# by properly terminating it at the card level. This guarantees that any power supply that monitors CARD_​CBL_​PRES# can detect the presence or absence of every connected PCIe card.
      • For modular power supplies, with “double-ended” 12V-2x6 cable assemblies, for example, this also confirms whether the 12V-2x6 cable plug connector is attached and fully seated in its mating 12V-2x6 PCB header connector in the power supply.
      • Consequently, any unused or incompletely seated 12V-2x6 connector in series between the PSU and the Add-in Card will de-assert CARD_​CBL_​PRES# and appear as unused or incompletely inserted.
  • Secondary Function:
    • This sideband signal can optionally provide additional communication between the Add-in Card, and PSU, and the host system to identify connectivity between any combination of 12V-2x6 and installed Add-in Card by means of the PCIe “Power Budgeting Sense Detect Register”. This allows the system to correlate which system and power cables are used with a specific PCIe* card slot. This function requires system-level integration with the motherboard that may lie beyond the scope of a standard ATX power supply. Card-level support for this secondary function is optional.

Note that CARD_​CBL_​PRES# is implemented only for system power supply management support. This signal cannot be used by the Add-in Card to determine the available power level, for example. Power limits are communicated separately from the power supply to the Add-in Card by the SENSE0 & SENSE1 signals. The CARD_​CBL_​PRES# conductor must traverse the length of the cable between the Add-in Card and the PSU. Support for this optional sideband signal does not directly rely on the other sideband signals defined for the 12V-2x6 connector and its can be implemented independently of other of these sideband signals.

CARD_​CBL_​PRES# Primary function (Optional on PSU, Required on Add-in Card)

Every Add-in Card mounting the 12V-2x6 PCB Header connector must terminate the CARD_​CBL_​PRES# conductor by tying its connector pin to ground through a 4.7 kΩ pull-down resistor. Since all Add-in Cards are required to implement this card presence logic, the CARD_​CBL_​PRES# signal will always be available to any PSU that implements the optional circuitry to monitor the state of the CARD_​CBL_​PRES# conductor.

Any power supply that (optionally) monitors CARD_​CBL_​PRES# must implement a high-impedance 3.3V logic compatible device input. The 4.7 kΩ on the Add-in Card serves as a strong pull-down, tying the CARD_​CBL_​PRES# to ground at the Add-in Card end of the cable. The pull-down should be implemented to present the active-low to the cable CARD_​CBL_​PRES# conductor even when no power is applied. For a power supply to detect the active low presence condition of the CARD_​CBL_​PRES# signal, a 100 kΩ (weak) pull-up resistor to 3.3 V is required within the PSU.

This allows the power supply to poll individual CARD_​CBL_​PRES# signals from separate 12V-2x6 cables to determine the presence (low impedance to ground) or absence (floating) of connected PCIe cards even before main power is applied to the 12V bus, and at any time thereafter. Any floating CARD_​CBL_​PRES# conductors will be pulled high to 3.3V by the detection circuitry in the PSU and recorded as unconnected cables, while conductors pulled low by the PCIe card termination will be detected as connected PCIe Add-in Cards. Knowledge of the quantity of connected devices can be used for PSU-level or system-wide power management, to selectively allocate power among multiple 12V-2x6 connectors using for example, by means of the SENSE0 and SENSE1 pins, before applying 12V power.

If this feature is used and the SENSE0 & SENSE1 signals are dynamically changed they must be changed only when the power supply is in Standby Mode (PS_​ON# is de-asserted and Main Power rails are not on). Once PS_​ON# becomes active and the main power rails achieve their full voltages, the SENSE0 & SENSE1 sideband signals must not change state.

Example: A power supply that has sufficient rated power, after satisfying other system power requirements, to deliver 600 watts to a single PCIe* Add-in Card could be configured, by means of SENSE0 and SENSE1, to support multiple topologies, following CARD_​CBL_​PRES# detection.

  • One PCIe* Add-in Card is detected, and that single card may draw 600 watts.
    1. Two PCIe* Add-in Cards are detected, and each card may draw 300 watts.
    2. Three or Four PCIe* Add-in Cards are detected, and each card may draw 150 watts.
    3. Five PCIe* cards are detected.
      • Four cards may draw 150 watts.
      • One card may draw 0 watt, since insufficient power is available after allocating to the other four cards at the lowest (150 watt) power levelNote that 0W is a valid configuration for a connected card. 0W is encoded with the “Open-Open” SENSE0-SENSE1 setting.

These combinations are provided as an example. It is important to recognize that power budgeting is often inexact, and many Add-in Cards will not consume 100% of the power allocated by SENSE0 and SENSE1 (150, 300, 450, or 600 watts).

In the example Case D, above, if the PSU designer or system integrator has specific knowledge that the power consumption of some (or all) of the Add-in Cards falls well below the full 150 watts, the SENSE0 and SENSE1 encoding may be configured to enable all five cards at 150 watts, instead of disabling one card at the 0W level to explicitly confine the total allocated power to 600 watts.

CARD_​CBL_​PRES# Secondary function (Optional)

The enumeration of connected PCIe Add-in Cards using CARD_​CBL_​PRES, as described above, identifies whether 12V2x6 cables are connected or unused. While this provides the quantity of connected cards, it does not convey any additional insight into the Add-in Card’s actual power consumption, function, or location (e.g., PCIe Slot 2).

The secondary function of the CARD_​CBL_​PRES# enables the system to map the connectivity of individual 12V-2x6 cables to specific PCIe Add-in Cards. Support for this secondary function requires deliberate chassis-level integration and communication with Add-in Cards through the system board. While support for this secondary function is currently beyond the scope of mainstream ATX power supply designs, it is not discouraged, and is included for completeness.

To support this secondary function, the power supply must selectively apply 3.3 V directly to the CARD_​CBL_​PRES# conductor for those cables whose connectivity is confirmed. The PSU is allowed to drive this signal high with a push-pull driver to 3.3V. This voltage defeats the 4.7 kΩ pull-down in the Add-in Card, driving CARD_​CBL_​PRES# to a logic high, which Add-in Cards may detect with optional circuitry.

When supporting the secondary function, the Add-in Card reads this signal on a high impedance 3.3V logic compatible input and records the logic high/low state in the “Power Budgeting Sense Detect” registers.

The intended use of this signal is to successively assert the CARD_​CBL_​PRES# conductor in individual 12V-2x6 cable connectors and then to read the Power Budgeting Sense Detect registers of the Add-in Cards (using custom hardware and software) to map the connectivity of the specific power cables to specific Add-in Card components. The function and location of the Add-in Cards must be identified separately, at the system level, to complete this mapping. The additional 12V-2x6 cable connectivity knowledge obtained can enable more nuanced chassis-level power management. Adoption of this capability will likely be confined to high-end server systems designed by system integrators or cloud service providers, for example.