Channels and Supported Transactions
An eSPI channel provides a means to allow multiple independent flows of traffic to share the same physical bus. Refer to the eSPI specification for more detail.
Each of the channels has its dedicated resources such as queue and flow control. There is no ordering requirement between traffic from different channels.
The number of types of channels supported by a particular eSPI slave is discovered through the GET_CONFIGURATION command issued by the PCH to the eSPI slave during initialization.
The table below summarizes the eSPI channels and supported transactions.
| CH # | Channel | Posted Cycles Supported | Non-Posted Cycles Supported |
|---|---|---|---|
| 0 | Peripheral | Memory Write, Completions | Memory Read, I/O Read/Write |
| 1 | Virtual Wire | Virtual Wire GET/PUT | N/A |
| 2 | Out-of-Band Message | SMBus Packet GET/PUT | N/A |
| 3 | Flash Access | N/A | Flash Read, Write, Erase |
| N/A | General | Register Accesses | N/A |
Peripheral Channel (Channel 0) Overview
The Peripheral channel performs the following functions:
- Target for PCI Device D31:F0: The eSPI controller duplicates the legacy LPC PCI Configuration space registers. These registers are mostly accessed via the BIOS, though some are accessed via the OS as well.
- Tunnel all Host to eSPI Slave (EC/SIO) Debug Device Accesses: These are the accesses that used to go over the LPC bus. These include various programmable and fixed I/O ranges as well as programmable Memory ranges. The programmable ranges and their enables reside in the PCI Configuration space.
- Tunnel all Accesses from the eSPI Slave to the Host: These include Memory Reads and Writes.
Virtual Wire Channel (Channel 1) Overview
The Virtual Wire channel uses a standard message format to communicate several types of signals between the components on the platform.
- Sideband and GPIO Pins: System events and other dedicated signals between the PCH and eSPI slave. These signals are tunneled between the 2 components over eSPI.
- Serial IRQ Interrupts: Interrupts are tunneled from the eSPI slave to the PCH. Both edge and triggered interrupts are supported.
- eSPI Virtual Wires (VW)
Table below summarizes the PCH virtual wires in eSPI mode.
eSPI Virtual Wires (VW)
Virtual Wire
PCH Pin Direction
Reset Control
Pin Retained in PCH (For Use by Other Components)
SUS_STAT#
Output
ESPI_RESET#
No
SUSWARN#
Output
ESPI_RESET#
No
SUS_ACK
Input
ESPI_RESET#
No
SUSPWRDNACK
Output
ESPI_RESET#
No
PLTRST#
Output
ESPI_RESET#
Yes
PME# (eSPI Peripheral PME)
Input
ESPI_RESET#
N/A
WAKE#
Input
ESPI_RESET#
No
SMI#
Input
PLTRST#
N/A
SCI#
Input
PLTRST#
N/A
RCIN#
Input
PLTRST#
No
SLP_A#
Output
ESPI_RESET#
Yes
SLP_S3#/SLP_S4#/SLP_S5#/SLP_LAN#/SLP_WLAN#
Output
DSW_PWROK
Yes
SLAVE_BOOT_LOAD_DONE
Input
ESPI_RESET#
N/A
SLAVE_BOOT_LOAD_STATUS
Input
ESPI_RESET#
N/A
HOST_RST_WARN
Output
PLTRST#
N/A
HOST_RST_ACK
Input
PLTRST#
N/A
OOB_RST_WARN
Output
ESPI_RESET#
N/A
OOB_RST_ACK
Input
ESPI_RESET#
N/A
HOST_C10
Output
PLTRST#
N/A
ERROR_NONFATAL
Input
ESPI_RESET#
N/A
ERROR_FATAL
Input
ESPI_RESET#
N/A
- Interrupt Events
eSPI supports both level and edge-triggered interrupts. Refer to the eSPI Specification for details on the theory of operation for interrupts over eSPI.
The PCH eSPI controller will issue a message to the PCH interrupt controller when it receives an IRQ group in its VW packet, indicating a state change for that IRQ line number.
The eSPI slave can send multiple VW IRQ index groups in a single eSPI packet, up to the Operating Maximum VW Count programmed in its Virtual Wire Capabilities and Configuration Channel.
The eSPI controller acts only as a transport for all interrupt events generated from the slave. It does not maintain interrupt state, polarity or enable for any of the interrupt events.
Out-of-Band Channel (Channel 2) Overview
The Out-of-Band channel performs the following functions:
- Tunnel MCTP Packets between the Intel® CSME and eSPI Slave Device: The Intel®CSME communicates MCTP messages to/from the device by embedding those packets over the eSPI protocol. This eliminates the SMBus connection between the PCH and the slave device which was used to communicate the MCTP messages in prior PCH generations. The eSPI controller simply acts as a message transport and forwards the packets between the Intel®CSME and eSPI device.
- Tunnel PCH Temperature Data to the eSPI Slave: The eSPI controller stores the PCH temperature data internally and sends it to the slave using a posted OOB message when a request is made to a specific destination address.
- Tunnel PCH RTC Time and Date Bytes to the eSPI Slave: the eSPI controller captures this data internally at periodic intervals from the PCH RTC controller and sends it to the slave device using a posted OOB message when a request is made to a specific destination address.
- PCH Temperature Data Over eSPI OOB Channel
eSPI controller supports the transmitting of PCH thermal data to the eSPI slave. The thermal data consists of 1 byte of PCH temperature data that is transmitted periodically (~1 ms) from the thermal sensor unit.
The packet formats for the temperature request from the eSPI slave and the PCH response back are shown in the two figures below.
eSPI Slave Request to PCH for PCH Temperature
PCH Response to eSPI Slave with PCH Temperature
- PCH RTC Time/Date to EC Over eSPI OOB Channel
The PCH eSPI controller supports the transmitting of PCH RTC time/date to the eSPI slave. This allows the eSPI slave to synchronize with the PCH RTC system time. Moreover, using the OOB message channel allows reading of the internal time when the system is in Sx states.
The RTC time consists of 7 bytes: seconds, minutes, hours, day of week, day of month, month and year. The controller provides all the time/date bytes together in a single OOB message packet. This avoids the boundary condition of possible roll over on the RTC time bytes if each of the hours, minutes, and seconds bytes is read separately.
The packet formats for the RTC time/date request from the eSPI slave and the PCH response back to the device are shown in the two figures below.
eSPI Slave Request to PCH for PCH RTC Time
PCH Response to eSPI Slave with RTC Time
Flash Access Channel (Channel 3) Overview
The Master Attached Flash Channel controller (MAFCC) tunnels flash accesses from eSPI slave to the PCH flash controller. The MAFCC simply provides Flash Cycle Type, Address, Length, Payload (for writes) to the flash controller. The flash controller is responsible for all the low level flash operations to perform the requested command and provides a return data/status back to the MAFCC, which then tunnels it back to the eSPI slave in a separate completion packet.
- Master Attached Flash Channel Controller (MAFCC) Flash Operations and Addressing
The EC is allocated a dedicated region within the eSPI Master-Attached flash device. The EC has default read, write, and erase access to this region.
The EC can also access any other flash region as permitted by the Flash Descriptor settings. As such, the EC uses linear addresses, valid up to the maximum supported flash size, to access the flash.
The MAFCC supports flash read, write, and erase operations only.
- Slave Attached Flash Channel Controller (SAFCC) Flash Operation and Addressing
The PCH is allocated dedicated regions (for each of the supported masters) within the eSPI slave-attached flash devices. The PCH has read, write, and erase access to these regions, as well as any other regions that maybe permitted by the region protections set in the Flash Descriptor.
The Slave will optionally performs additional checking on the PCH provided address. In case of an error due to incorrect address or any other issues it will synthesize an unsuccessful completion back to the eSPI Master.
The SAFCC supports Flash Read, Write and Erase operations. It also supports Read SFDP and Read JEDEC ID commands as specified in the eSPI Specification for Server platforms.